ASIC Physical Design Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
Singapore
Embedded
Senior Software Engineer
In-Person
5+ years of experience
Enterprise SaaS

Description For ASIC Physical Design Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior ASIC Physical Design Engineer for their Singapore office. This role focuses on advanced semiconductor design using cutting-edge process technologies (7nm to 2nm). The position requires expertise in EDA tools from industry leaders like Synopsys, Cadence, and Siemens, handling complex digital blocks and full Netlist/Gates to GDS flow implementation.

The ideal candidate will have at least 5 years of experience in ASIC physical design, with strong educational background in Electrical, Electronics, or Computer Engineering. You'll be working on sophisticated integrated circuits with 100-400 million gates, requiring deep technical knowledge in various aspects of chip design including RTL synthesis, placement, clock tree synthesis, and verification.

This is an excellent opportunity for experienced engineers looking to work with advanced semiconductor technologies at a company that's at the forefront of technological innovation. You'll be part of a team that develops crucial components for modern computing infrastructure, working with state-of-the-art tools and processes.

The role offers the chance to work on challenging projects that push the boundaries of semiconductor technology, requiring both technical expertise and the ability to manage multiple complex assignments simultaneously. At Broadcom, you'll be contributing to products that power the future of technology while working in an inclusive environment that values diversity and innovation.

Last updated 4 minutes ago

Responsibilities For ASIC Physical Design Engineer

  • Utilize commercial and in-house EDA tools for design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies
  • Handle full Netlist/Gates to GDS flow, including RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis
  • Manage complex digital blocks of up to 12Mgates/3M instances with embedded macros
  • Handle multiple block assignments in parallel

Requirements For ASIC Physical Design Engineer

Linux
  • Degree, Masters or PhD in Electrical/Electronics/Computer engineering
  • Minimum of 5 years or more experience in a relevant field
  • Proficiency in UNIX/Linux and scripting languages

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