ASIC Physical Design Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions
Singapore
Embedded
Senior Software Engineer
In-Person
5+ years of experience
Enterprise SaaS

Description For ASIC Physical Design Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking an experienced ASIC Physical Design Engineer to join their team in Singapore. This role focuses on designing and implementing complex integrated circuits using cutting-edge process technologies from 7nm down to 2nm. The position requires expertise in handling sophisticated digital blocks and utilizing industry-standard EDA tools from vendors like Synopsys, Cadence, and Siemens.

The ideal candidate will be responsible for managing the complete Netlist/Gates to GDS flow, working with blocks containing up to 12Mgates/3M instances with embedded macros. This challenging role requires strong technical skills in RTL synthesis, placement, clock tree synthesis, detailed routing, and various verification processes. The ability to handle multiple block assignments simultaneously is crucial for success in this position.

Broadcom offers an inclusive work environment, considering qualified applicants regardless of their background, and provides opportunities to work with advanced semiconductor technologies. The company's strong presence in the global technology market and commitment to innovation makes this an excellent opportunity for experienced engineers looking to work on cutting-edge semiconductor designs.

This role combines technical expertise with practical implementation skills, requiring both educational qualifications and substantial industry experience. The position offers the chance to work with state-of-the-art tools and technologies while contributing to Broadcom's mission of delivering innovative semiconductor solutions.

Last updated a day ago

Responsibilities For ASIC Physical Design Engineer

  • Utilize commercial and in-house EDA tools for design and implementation of 100-400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies
  • Handle full Netlist/Gates to GDS flow including RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis
  • Manage complex digital blocks up to 12Mgates/3M instances with embedded macros
  • Handle multiple block assignments in parallel

Requirements For ASIC Physical Design Engineer

Linux
  • Degree, Masters or PhD in Electrical/Electronics/Computer engineering
  • Minimum of 5 years or more experience in a relevant field
  • Proficiency in UNIX/Linux and scripting languages
  • Experience with Synopsys, Cadence, Siemens EDA tools

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