Design Engineer - STA
Description For Design Engineer - STA
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior Static Timing Analysis (STA) Design Engineer to join their team. This role combines deep technical expertise in VLSI and ASIC physical design with advanced understanding of timing analysis concepts.
The position requires a seasoned professional with either a BS degree and 12+ years of experience or an MS degree with 10+ years of experience in Electrical or Computer Engineering. The ideal candidate will possess strong knowledge of static timing analysis tools, particularly Synopsys PrimeTime and Cadence Tempus, along with expertise in debugging timing constraints and analyzing complex timing scenarios.
Key responsibilities include creating and debugging timing constraints, generating comprehensive timing reports, and performing various types of timing analysis including setup, hold, and signal integrity checks. The role demands strong problem-solving abilities and excellent communication skills to work effectively with cross-functional teams across different geographical locations.
The position offers a competitive compensation package ranging from $127,000 to $203,000 annually, plus discretionary bonus and equity opportunities. Broadcom provides comprehensive benefits including medical, dental, and vision coverage, 401(k) with company matching, ESPP, and various leave benefits.
This is an excellent opportunity for an experienced engineer looking to work with cutting-edge semiconductor technology while solving complex timing challenges in a collaborative environment. The role offers significant technical depth and the chance to work with advanced tools and methodologies in the semiconductor industry.
Responsibilities For Design Engineer - STA
- Create and debug timing constraints
- Generate and analyze timing reports
- Perform setup analysis, hold analysis, and other timing checks
- Work with and organize large amounts of data
- Coordinate with multiple engineers and teams across geographies
- Create and understand timing diagrams
- Manage various tasks related to Static Timing Analysis
Requirements For Design Engineer - STA
- BS in Electrical Engineering or Computer Engineering with 12+ years experience or MS with 10+ years experience
- Strong understanding of VLSI and ASIC physical design
- Understanding of PLLs and clock networks
- Experience with static timing analysis tools (Synopsys PrimeTime, Cadence Tempus)
- Strong understanding of RC networks and timing/propagation of signals
- Experience with SPICE analysis
- TCL programming experience required
- Strong debugging and problem-solving abilities
- Ability to work with teams across different geographies
Benefits For Design Engineer - STA
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays, sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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