Design Verification and DFT Engineer
Description For Design Verification and DFT Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Design Verification and DFT Engineer to join their Central Engineering Group. This role is integral to their memory subsystem design team, focusing on developing large memory blocks and subsystems. The position offers a competitive salary range of $91,000 - $146,000 plus comprehensive benefits.
The ideal candidate will have 5+ years of experience and a strong background in electrical engineering, particularly in Verilog and system Verilog. You'll be responsible for creating test plans, implementing testbenches, debugging simulation issues, and working on DFT deliverables. The role requires expertise in Universal Verification Methodology (UVM) and system Verilog assertions.
This is an excellent opportunity for someone passionate about hardware verification and design for testability. You'll work with cutting-edge technology in memory systems while collaborating with talented design engineers. The position offers growth potential within a leading technology company, competitive compensation, and comprehensive benefits including medical coverage, 401(k) matching, and equity opportunities.
Broadcom's inclusive culture values diversity and promotes equal opportunities for all qualified candidates. The company offers a supportive work environment with opportunities for professional development and advancement. Join a team that's pushing the boundaries of semiconductor technology and making a significant impact in the industry.
Responsibilities For Design Verification and DFT Engineer
- Work with design engineers to create test plans
- Implement Verilog testbenches
- Debug simulation errors and issues
- Work with design engineers to implement assertions and check coverage
- Create and verify DFT deliverables
Requirements For Design Verification and DFT Engineer
- Bachelor in Electrical Engineering
- Good understanding of Verilog and system Verilog
- Good understanding of Universal Verification Methodology (UVM)
- Understanding of system Verilog assertions
- Familiar with memory behavior
- Good understanding of DFT schemes and chip level integration
- Proficient in running simulators, writing automation scripts, and are tools savvy
- Good communication, interpersonal, and leadership skills
- Motivated, self-driven and good at multitasking
Benefits For Design Verification and DFT Engineer
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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