Design Verification Engineer
Description For Design Verification Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior Design Verification Engineer to join their team in the San Francisco Bay Area. This role focuses on functional verification of complex designs, particularly around external interfacing IPs. The ideal candidate will have 8+ years of experience with a strong background in verification methodologies like UVM and expertise in System Verilog.
The position offers a competitive compensation package ranging from $107,000 to $171,000 annually, plus discretionary bonuses and equity opportunities. You'll be responsible for all aspects of verification, from test planning to coverage closure, and will work with cutting-edge technologies in areas such as High bandwidth memory, Ethernet/PCIE/CXL, and Serdes designs.
Broadcom provides comprehensive benefits including medical, dental, and vision coverage, 401(k) matching, ESPP, and various leave policies. The company values diversity and maintains an inclusive work environment. This is an excellent opportunity for experienced verification engineers looking to work on challenging projects at a leading technology company.
The role requires expertise in architecting reusable test benches, strong understanding of System Verilog assertions, and the ability to support external customers. You'll be part of a team working on innovative solutions in the semiconductor industry, with opportunities for professional growth and development.
Responsibilities For Design Verification Engineer
- Functional verification of complex designs, especially around external interfacing IPs
- Test planning, test bench development, test execution
- Functional/code coverage closure
- External customer support for design IPs or VIPs
Requirements For Design Verification Engineer
- Expertise in architecting reusable and constrained random test benches from scratch
- Expertise in UVM verification methodologies
- Strong understanding of System Verilog assertions
- Ability to understand Verilog designs and develop verification properties
- Verification expertise with Interface IP designs
- Bachelor's Degree + 8+ years of experience or Master's Degree + 6+ years of experience
Benefits For Design Verification Engineer
- Medical, dental and vision plans
- 401(K) participation with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
Jobs Related To Broadcom Design Verification Engineer
