Design Verification Engineer
Description For Design Verification Engineer
Broadcom's ASIC Product Division is seeking a Design Verification Engineer to join their high-performance team developing state-of-the-art SoC and embedded IP. This senior role involves advanced verification tasks using modern techniques and tools. The position offers a competitive salary range of $141,000 - $225,000 plus comprehensive benefits. The ideal candidate will have 12+ years of experience in ASIC design verification, strong knowledge of System Verilog, UVM, and debugging capabilities. You'll work on cutting-edge subsystem development, implementing verification environments, and ensuring quality through thorough testing and analysis. The role combines technical expertise with collaborative teamwork, offering opportunities to work on advanced semiconductor solutions. Broadcom provides a supportive environment with excellent benefits including medical coverage, 401(k) matching, and equity participation. This is an excellent opportunity for experienced verification engineers looking to work with a global technology leader in semiconductor development.
Responsibilities For Design Verification Engineer
- Verification environment development using modern verification techniques
- Designing verification components such as UVM agents and behavioral models
- Implementing coverage and assertions using System Verilog
- Developing random & directed test cases against the specification
- Analyzing and debugging simulation failures
- Analyzing coverage results
Requirements For Design Verification Engineer
- Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
- 12+ years relevant industry work experience
- Experience in verifying designs at system level and block level
- Fluent knowledge of RTL verification methodologies including System Verilog
- Strong experience in ASIC design verification flows and DV methodologies
- Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills
- Strong and independent design debugging capability
- Strong verbal and written communication skills
- Must have legal authorization to work in the US
Benefits For Design Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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