Design Verification Engineer
Description For Design Verification Engineer
Broadcom's ASIC Product Division is seeking a Design Verification Engineer to join their high-performance team developing state-of-the-art SoC and embedded IP. This senior role requires 8+ years of experience and deep expertise in verification methodologies. You'll be responsible for advanced verification tasks using System Verilog and UVM, designing verification components, and ensuring quality through comprehensive testing and debugging.
The position offers a competitive salary range of $119,000 - $190,000, along with comprehensive benefits including medical, dental, vision insurance, 401(k) matching, and equity opportunities. You'll work with cutting-edge technology in semiconductor and infrastructure software solutions, contributing to system and sub-block level verification.
The ideal candidate will have a Bachelor's degree in Electrical Engineering or Computer Science, strong experience with ASIC design verification flows, and expertise in object-oriented verification languages. Additional valuable skills include experience with hardware design, C++/SystemC, and FPGA-based prototyping.
Working at Broadcom means joining a global technology leader with a strong focus on innovation. You'll be part of a collaborative team environment, working on challenging projects that push the boundaries of semiconductor technology. The company offers professional growth opportunities and a supportive culture that values technical excellence and creative problem-solving.
This role is perfect for a seasoned verification engineer who enjoys complex technical challenges and wants to work with industry-leading technology. You'll have the opportunity to impact critical projects while working with a talented team in a stable, growing company.
Responsibilities For Design Verification Engineer
- Verification environment development using modern verification techniques (System Verilog and UVM)
- Designing verification components such as UVM agents and behavioral models
- Implementing coverage and assertions using System Verilog
- Developing random & directed test cases against the specification
- Analyzing and debugging simulation failures
- Analyzing coverage results
Requirements For Design Verification Engineer
- Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
- 8+ years relevant industry work experience
- Experience in verifying designs at system level and block level
- Fluent knowledge of RTL verification methodologies including System Verilog
- Strong experience in ASIC design verification flows and DV methodologies
- Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills
- Strong and independent design debugging capability
- Strong verbal and written communication skills
- Must have legal authorization to work in the US
Benefits For Design Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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