DFT Engineer

Global technology leader designing and developing semiconductor and infrastructure software solutions.
$141,000 - $225,000
Embedded
Principal Software Engineer
In-Person
5,000+ Employees
12+ years of experience
Enterprise SaaS

Description For DFT Engineer

Broadcom's ASIC Product Division is seeking a Principal DFT Engineer to lead DFT programs from chip level specification through implementation and verification. This role involves working on various phases of SoC DFT activities for the ASIC Products Division, including DFT Architecture, Test insertion and verification, Pattern generation, and Post silicon debug. The position requires expertise in implementing DFT features, working with Physical Design & STA teams, and interacting with external customers. The role combines technical leadership with hands-on engineering, requiring proficiency in programming languages like TCL, PERL, RUBY, PYTHON, or C++. This is an opportunity to work on cutting-edge semiconductor technology at 7nm and beyond, with competitive compensation and comprehensive benefits.

Last updated 12 days ago

Responsibilities For DFT Engineer

  • Understanding DFT feature requirements & DPPM goals & defining DFT specifications for ASIC
  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
  • Working with STA and DI Engineers for design closure for test
  • Generating, Verifying & Debugging Test vectors
  • Validating & Debugging Test vectors on ATE during silicon bring up
  • Assisting with silicon failure analysis, diagnostics & yield improvement
  • Interfacing with customer, physical design and test engineering teams globally
  • Debugging customer returned parts on the ATE
  • Innovating newer DFT solutions for 7nm & beyond
  • Automating DFT & Test Vector Generation flows

Requirements For DFT Engineer

Python
Ruby
  • Strong DFT background in IO and Analog DFT, ATPG, Scan, BIST
  • Experience with scan insertion and compression (DFT Compiler, Mentor TestKompress)
  • Expertise in ATPG vector generation, simulation, and debugging
  • Verilog coding, testbench generation & simulation experience
  • Memory BIST insertion and verification experience
  • Knowledge of IEEE1149.1 and IEEE1149.6
  • Strong background in IEE1687, IJTAG, ICL and PDL
  • Bachelor's or Master's in Electrical/Electronic/Computer Engineering
  • 12+ years experience with Bachelor's or 10+ years with Master's
  • Knowledge in analog and digital circuit design
  • Understanding of Si processing and transistor reliability principles
  • Excellent problem solving and communication skills

Benefits For DFT Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Parental Leave
  • Medical, dental and vision plans
  • 401(K) participation with company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Paid holidays, sick leave and vacation time
  • Paid Family Leave
  • Discretionary annual bonus
  • Equity compensation

Interested in this job?

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