DFT Engineer
Description For DFT Engineer
Broadcom's CSG division is seeking a senior DFT (Design for Test) Engineer to lead cutting-edge network switching ASIC development. This role combines hardware engineering expertise with software tools to ensure product quality and manufacturability. The position offers an opportunity to work with state-of-the-art technology in semiconductor design and testing, while contributing to critical quality assurance processes.
The role involves leading complex DFx (Design for Test/debug & manufacturability) implementations from architecture to verification. You'll be responsible for driving innovation in testability, debug, and quality optimization, while managing cost-effectiveness. This position requires deep technical knowledge in various testing methodologies and tools, including SCAN, Built-in-Self-Tests, and Loop-Backs.
As a DFT Engineer at Broadcom, you'll work with industry-leading tools from Mentor/Siemens and Cadence, implementing sophisticated testing solutions for digital logic, embedded memories, and PHY/IOs. The role offers competitive compensation, comprehensive benefits, and the opportunity to work with a global technology leader in semiconductor development.
The ideal candidate will combine strong technical expertise with excellent communication and project management skills. With 8+ years of experience required, this position offers significant responsibility and the chance to impact product quality from design through production. Join Broadcom to be part of a team driving innovation in semiconductor testing and quality assurance.
Responsibilities For DFT Engineer
- Drive the test quality of the products from Design to Production
- Participate/contribute in silicon bring-up, characterization, and silicon test
- Define and implement various DFx features
- Lead complex network switching ASIC DFx implementation
- Drive state of the art testability, debug and quality optimization
Requirements For DFT Engineer
- Knowledge of Testability techniques (SCAN, Built-in-Self-Tests, Loop-Backs)
- Experience with Mentor/Siemens DFT Tessent tool
- Experience with Cadence DFT tools (Modus and Genus)
- Knowledge of JTAG/1500/1687 networks and BSDL, ICL and PDL
- Strong knowledge of logic & circuit design fundamentals
- Working knowledge of TCL, perl
- Experience in MBIST implementation for memories
- Strong Pre/Post Silicon debugging and analytical skills
- Bachelor's degree with 8+ years of related experience
- Must be a team player with good communication skills
Benefits For DFT Engineer
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays, sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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