DFT Engineer
Description For DFT Engineer
Broadcom's ASIC Product Division is seeking an experienced Principal DFT Engineer to lead their DFT programs at their San Jose facility. This role represents a unique opportunity to work with cutting-edge semiconductor technology, focusing on chip-level DFT specification through implementation and verification.
The position involves comprehensive work on various phases of SoC DFT-related activities for Broadcom's ASIC Products Division designs. Key responsibilities include DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, and Post silicon debug. The role requires collaboration with Physical Design & STA teams for DFT mode timing closure and direct interaction with external customers.
The ideal candidate will bring 12+ years of experience (with BS) or 10+ years (with MS) in Electrical/Electronic/Computer Engineering, demonstrating deep expertise in DFT background, including IO and Analog DFT, ATPG, Scan, and BIST. Technical proficiency in various tools and technologies is essential, including scan insertion, compression techniques, and programming languages such as TCL, PERL, RUBY, PYTHON, or C++.
Broadcom offers a competitive compensation package, including a base salary range of $141,000 - $225,000, plus discretionary annual bonus and equity awards. The comprehensive benefits package includes medical, dental, vision coverage, 401(k) with company matching, ESPP, and various leave benefits. The company culture promotes innovation, collaboration, and professional growth while working on advanced semiconductor technologies.
This role presents an excellent opportunity for a seasoned professional to make significant contributions to Broadcom's semiconductor technology advancement while working with a global team of experts in the field.
Responsibilities For DFT Engineer
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining DFT specifications for ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors
- Validating & Debugging Test vectors on ATE during silicon bring up
- Assisting with silicon failure analysis, diagnostics & yield improvement
- Interfacing with customer, physical design and test engineering teams globally
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions for 7nm & beyond
- Automating DFT & Test Vector Generation flows
Requirements For DFT Engineer
- Bachelor's or Master's in Electrical/Electronic/Computer Engineering
- 12+ years experience (BS) or 10+ years experience (MS)
- Strong DFT background (IO and Analog DFT, ATPG, Scan, BIST)
- Experience with scan insertion and compression (DFT Compiler, Mentor TestKompress)
- Proficiency in ATPG vector generation, simulation, and debugging
- Verilog coding, testbench generation & simulation experience
- Memory BIST insertion and verification experience
- Knowledge of IEEE1149.1 and IEEE1149.6
- Strong background in IEE1687, IJTAG, ICL and PDL
- Programming skills in TCL, PERL, RUBY, PYTHON, or C++
- Excellent problem solving and communication skills
Benefits For DFT Engineer
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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