HBM/DDR/SERDES DFT Verification Lead Engineer
Description For HBM/DDR/SERDES DFT Verification Lead Engineer
Broadcom's ASIC Product Division is seeking a highly skilled HBM/DDR/SERDES DFT Verification Lead Engineer at their San Jose facility. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies. The position offers an opportunity to work with cutting-edge technology in semiconductor design, particularly in high-speed interfaces and memory systems. The role combines technical leadership with hands-on engineering, requiring expertise in both digital and analog domains. The successful candidate will collaborate with global teams, drive innovation in DFT solutions, and contribute to next-generation semiconductor technologies. With a competitive compensation package including equity and comprehensive benefits, this position offers an excellent opportunity for experienced engineers looking to make a significant impact in semiconductor verification and testing.
Responsibilities For HBM/DDR/SERDES DFT Verification Lead Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for design improvements
- Document verification processes, results, and best practices
- Work with STA and DI Engineers for test design closure
- Generate, verify & debug test vectors before tape release
- Validate & debug test vectors on ATE during silicon bring up
- Assist with silicon failure analysis and yield improvement
- Interface with customers and global engineering teams
- Debug customer returned parts on ATE
- Innovate DFT solutions for 3nm IPs & beyond
- Automate DFT & Test Vector Generation flows
Requirements For HBM/DDR/SERDES DFT Verification Lead Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting (Perl, Python, TCL, Ruby)
- Excellent analytical and problem-solving skills
- Strong communication and teamwork abilities
- Solid knowledge in analog and digital circuit design
- Bachelor's in Electrical/Electronic/Computer Engineering with 12+ years experience or Master's with 10+ years experience
Benefits For HBM/DDR/SERDES DFT Verification Lead Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual bonus
- Equity awards
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