HBM/DDR/SERDES DFT Verification Lead Engineer
Description For HBM/DDR/SERDES DFT Verification Lead Engineer
Broadcom's ASIC Product Division is seeking a HBM/DDR/SERDES DFT Verification Lead Engineer for their San Jose location. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test verification strategies. The position offers a competitive salary range of $107,000 - $190,000 with additional benefits including equity and bonuses.
The ideal candidate will have 8+ years of experience with a Bachelor's degree or 6+ years with a Master's in Electrical/Electronic/Computer Engineering. Key responsibilities include implementing DFT methodologies, collaborating with cross-functional teams, and working on cutting-edge 3nm IPs and beyond.
The role requires strong technical expertise in DFT verification, particularly with HBM, DDR, PCIE, and SerDes IPs, along with proficiency in various programming languages and simulation tools. The position offers growth opportunities within a global technology leader that designs and develops semiconductor and infrastructure software solutions.
Working at Broadcom provides comprehensive benefits including medical coverage, 401(k) matching, stock purchase options, and work-life balance through paid time off and family leave policies. The company promotes an inclusive environment and considers qualified applicants regardless of background.
Responsibilities For HBM/DDR/SERDES DFT Verification Lead Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize advanced simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for design improvements
- Document verification processes, results, and best practices
- Work with STA and DI Engineers for test design closure
- Generate, verify & debug test vectors before tape release
- Validate & debug test vectors on ATE during silicon bring up
- Interface with customers, physical design and test teams globally
- Debug customer returned parts on the ATE
- Automate DFT & Test Vector Generation flows
Requirements For HBM/DDR/SERDES DFT Verification Lead Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting (Perl, Python, TCL, Ruby)
- Knowledge in analog and digital circuit design
- Excellent problem solving and debug skills
- Bachelor's in Electrical/Electronic/Computer Engineering with 8+ years experience or Master's with 6+ years experience
- Strong communication and teamwork abilities
Benefits For HBM/DDR/SERDES DFT Verification Lead Engineer
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays, sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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