IC Design Engineer
Description For IC Design Engineer
Broadcom is seeking an IC Design Engineer to work on various phases of SOC physical design activities. The role involves block level tasks such as floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification (LVS/DRC/ERC/Antenna etc.). The candidate should be able to meet congestion, timing, and area metrics, and perform equivalence checks, STA, crosstalk delay analysis, noise analysis, and power optimization. They should be capable of implementing timing and functional ECOs.
Key responsibilities include:
- Working on SOC physical design activities
- Meeting congestion, timing, and area metrics
- Performing various analyses and optimizations
- Implementing ECOs
- Problem-solving for congestion resolution and timing closure
- Formal verification and timing analysis
The ideal candidate should have experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, and Primetime. They should be able to work independently, guide team members, and adapt to new tools and methodologies. Experience working in a global team and dynamic environment is essential.
Broadcom offers a diverse and inclusive work environment, considering qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other protected characteristic.
Join Broadcom to be part of a global technology leader and contribute to cutting-edge semiconductor and software solutions.
Responsibilities For IC Design Engineer
- Work on various phases of SOC physical design activities
- Perform block level tasks including floor-planning, partitioning, placement, and clock tree synthesis
- Conduct physical verification (LVS/DRC/ERC/Antenna)
- Meet congestion, timing, and area metrics
- Perform equivalence checks, STA, crosstalk delay analysis, and noise analysis
- Implement timing and functional ECOs
- Optimize power consumption
- Resolve congestion and achieve timing closure
- Conduct formal verification and timing analysis
- Guide and support other team members
- Adapt to new tools and methodologies as needed
Requirements For IC Design Engineer
- Experience in SOC physical design activities
- Proficiency in floor-planning, partitioning, placement, clock tree synthesis, and routing
- Knowledge of physical verification (LVS/DRC/ERC/Antenna)
- Experience with equivalence checks, STA, crosstalk delay analysis, and noise analysis
- Ability to implement timing and functional ECOs
- Problem-solving skills for congestion resolution and timing closure
- Experience with formal verification and timing analysis
- Familiarity with tools such as Innovus/Encounter, ICC, Caliber, LEC, and Primetime
- Ability to work independently and guide team members
- Experience working in a global team and dynamic environment
- Adaptability to new tools and methodologies
- Excellent communication skills
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