IC Design Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
$119,000 - $190,000
Embedded
Senior Software Engineer
In-Person
12+ years of experience
Enterprise SaaS

Description For IC Design Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking an experienced IC Design Engineer to join their team. This role offers an exciting opportunity to work on cutting-edge semiconductor technology with a focus on RTL design and low-power implementations.

The position requires a seasoned professional with 12+ years of experience in IC design, offering a competitive salary range of $119,000 to $190,000, along with comprehensive benefits including medical coverage, 401(k) matching, and equity compensation. Based in San Jose, CA, you'll be part of a dynamic team working on sophisticated semiconductor solutions.

As an IC Design Engineer, you'll be responsible for critical aspects of chip design, from architectural definition to silicon bring-up. Key responsibilities include RTL design using Verilog HDL, implementing multi-power designs, and collaborating with verification and physical design teams. You'll work with various technologies including ARM CPUs, memory controllers, and various peripheral interfaces.

The ideal candidate will bring strong expertise in logic design and RTL coding, with a deep understanding of low-power design techniques and validation. Experience with ARM architectures, memory controllers, and protocols like I2C, SPI, and UART is highly valued. The role offers opportunities to work with cutting-edge technology while contributing to Broadcom's innovative semiconductor solutions.

This position is perfect for a self-motivated professional who excels in both independent work and cross-functional collaboration. You'll be part of a global technology leader that values innovation and technical excellence, with opportunities for professional growth and development. The comprehensive benefits package, competitive compensation, and chance to work on industry-leading semiconductor solutions make this an attractive opportunity for experienced IC design professionals looking to make a significant impact in the semiconductor industry.

Last updated 4 days ago

Responsibilities For IC Design Engineer

  • Participate in IP level architectural definition including micro-architecture definition
  • Perform RTL design using Verilog HDL, with emphasis on performance and area
  • Implement multi-power and low-power designs
  • Analyze and resolve Lint and Clock/Reset Domain crossing issues
  • Collaborate with verification team on test plan development, debugging, and coverage closure
  • Collaborate with physical design team on constraint generation, timing closure analysis
  • Support system level validation efforts on FPGA/emulation
  • Support silicon bring-up and debug efforts

Requirements For IC Design Engineer

Python
Linux
  • BS+12 Years of relevant industry experience. Advanced degree preferred
  • Strong Logic Design, RTL coding (Verilog HDL) and debugging skills
  • Understanding of low power design and validation techniques including UPF/CPF
  • Familiar with design constraint generation, logic synthesis, timing closure analysis
  • Experience with ARM CPUs
  • Experience with memory controllers
  • Knowledge of peripherals such as I2C, SPI and UART
  • Experience with peripherals and interconnect protocols (APB, AHB, AXI)
  • Self-motivated with ability to work independently
  • Good verbal and written communication skills
  • Ability to work with remote and cross functional teams

Benefits For IC Design Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Mental Health Assistance
Equity
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave and vacation time
  • Paid Family Leave
  • Annual discretionary bonus
  • Equity compensation

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