IC Verification Engineer
Description For IC Verification Engineer
Broadcom, a global leader in semiconductor and software solutions, is seeking a Senior IC Verification Engineer for their high-speed interconnect products team. This role focuses on verifying advanced communications networks products operating at speeds over 100Gbps, including Ethernet, PCIe, and Optical Transport physical layer devices. The position offers comprehensive benefits and competitive compensation ranging from $107,000 to $171,000 annually.
The ideal candidate will have 8+ years of experience in ASIC design and verification, with expertise in SystemVerilog and UVM. You'll be responsible for architecting verification environments, developing test plans, and ensuring product quality through various testing methodologies. The role involves working with cutting-edge technology in 100Gbs/200Gbs/400Gbs/800Gbs Ethernet and Gen5/Gen6 PCIe systems.
This is an excellent opportunity for experienced verification engineers looking to work on complex, high-impact projects. You'll be part of a team developing next-generation communication technologies while having the chance to mentor junior engineers. The position offers both technical challenges and leadership opportunities, making it ideal for those looking to advance their careers in hardware verification.
The role comes with a comprehensive benefits package including medical, dental, and vision insurance, 401(k) matching, equity compensation, and various other perks. Located in Austin, Texas, you'll be working in one of America's most dynamic tech hubs. Join Broadcom to be part of a company that's driving innovation in high-speed communication technologies and making a significant impact in the semiconductor industry.
Responsibilities For IC Verification Engineer
- Architect and develop verification environment and testbench components such as BFMs and checkers
- Develop comprehensive test plan and implement test cases
- Verify design in block and chip level environment using directed and constrained random testing
- Perform RTL code coverage, assertion coverage, and gate level simulations
- Drive and adopt new verification methodologies and flows for efficiency improvements
- Mentor junior engineers on project execution
Requirements For IC Verification Engineer
- MSEE plus 6 years, or BSEE plus 8 years, equivalent experience in ASIC design and verification
- Experience in verifying designs at system level and block level
- Experience using SystemVerilog and UVM
- Familiar with System Verilog Assertions
- Strong experience in ASIC design verification flows and DV methodologies
- Networking domain knowledge (e.g. Ethernet, GFP, OTN)
- Strong and independent design debugging capability
- Strong programming and scripting language capability
- Highly motivated and be able to work both independently and as a member of team
Benefits For IC Verification Engineer
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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