IP Integration Lead Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
Fort Collins, CO, USA
$91,000 - $146,000
Embedded
Senior Software Engineer
In-Person
5+ years of experience
Enterprise SaaS · AI

Description For IP Integration Lead Engineer

Broadcom's ASIC Product Division (APD) is seeking an IP Integration Lead Engineer to join their team in Fort Collins, CO. This role is crucial in developing die-to-die PHY IP for custom silicon ASIC products. The position involves working with cutting-edge technology in 2.5D and 3DIC ASICS, making it an exciting opportunity for experienced engineers.

The role combines technical expertise in ASIC design with leadership responsibilities, requiring both independent work and team collaboration. You'll be working with cross-functional teams including analog design, digital design, physical composition, DFT, timing, and customers. The position offers competitive compensation ranging from $91,000 to $146,000 annually, plus bonus and equity opportunities.

Broadcom provides a comprehensive benefits package and works on projects spanning from cloud computing AI engines to supercomputers and advanced wireless solutions. This is an excellent opportunity for someone with strong ASIC design experience who wants to work with leading-edge technology in a collaborative environment.

The ideal candidate will have deep understanding of ASIC design flow, experience with industry-standard tools like Cadence Innovus, and strong communication skills. The role offers the chance to work on complex technical challenges while developing and implementing critical methodologies for large-scale ASIC integration.

Last updated 2 days ago

Responsibilities For IP Integration Lead Engineer

  • Develop detailed understanding of Broadcom's die-to-die PHYs
  • Work and coordinate with multiple cross functional teams to build PHYs
  • Work with physical composition teams and interposer design teams to optimize signal IO patterns and escapes
  • Work with analog and physical composition teams to optimize size and power delivery to high IO density PHYs
  • Work with teams to analyze power integrity in various use cases and workloads
  • Develop/write PHY integration documentation for ASIC composition teams
  • Develop list of Checklist task for integration of PHY IP into ASICS
  • Work with IP build teams to complete quality crosschecks
  • Help support customer and ASIC PHY integration questions

Requirements For IP Integration Lead Engineer

Python
Ruby
Linux
  • Bachelor's Degree in Electrical and Electronic Engineering or equivalent and 5+ years of experience or Masters degree and 3+ years of experience
  • Understanding of design trade offs for power, area, and speed in ASIC designs
  • Understanding of complex issues related to timing closure, power integrity and signal integrity
  • Firm understanding of ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC
  • Experience with Cadence Innovus or equivalent toolset
  • Strong verbal, written communication, and presentation skills
  • Well organized, methodical, and detail oriented
  • Must develop, accurately track, and meet commitments to product engineering development schedules

Benefits For IP Integration Lead Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Mental Health Assistance
Equity
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave and vacation time
  • Paid Family Leave
  • Annual discretionary bonus
  • Equity compensation

Interested in this job?

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