IP Integration Lead Engineer

Global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
Fort Collins, CO, USA
$146,000 - $234,000
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
15+ years of experience
Enterprise SaaS · AI

Description For IP Integration Lead Engineer

Broadcom's ASIC Product Division (APD) is seeking an IP Integration Lead Engineer to join their team in Fort Collins, CO. This role is crucial in developing die-to-die PHY IP for custom silicon ASIC products. The position involves working with cutting-edge technology in 2.5D and 3DIC ASICS, requiring expertise in physical composition and integration methodologies.

The ideal candidate will be part of a cross-functional team, working on complex semiconductor solutions that power everything from cloud computing AI engines to advanced wireless solutions. This role offers an opportunity to work with bleeding-edge intellectual property and contribute to products that maintain a sustainable competitive advantage in the market.

Key responsibilities include optimizing signal IO patterns, managing power delivery systems, and coordinating with various teams including analog design, digital design, and physical composition. The role requires both technical expertise and strong communication skills, as you'll be developing integration documentation and supporting customer inquiries.

The position offers a competitive compensation package ranging from $146,000 to $234,000, plus bonus and equity opportunities. Broadcom provides comprehensive benefits including medical coverage, 401(k) matching, and stock purchase programs. This is an excellent opportunity for experienced professionals looking to work with advanced semiconductor technology in a collaborative environment.

Last updated 20 days ago

Responsibilities For IP Integration Lead Engineer

  • Develop detailed understanding of Broadcom's die-to-die PHYs
  • Coordinate with cross functional teams to build PHYs
  • Work with physical composition teams to optimize signal IO patterns and escapes
  • Optimize size and power delivery to high IO density PHYs
  • Analyze power integrity in various use cases and workloads
  • Develop PHY integration documentation
  • Develop integration checklist tasks
  • Support customer and ASIC PHY integration questions

Requirements For IP Integration Lead Engineer

Python
Ruby
  • Bachelor's Degree in Electrical and Electronic Engineering or equivalent and 15+ years of experience (or Masters with 13+ years)
  • Understanding of design trade offs for power, area, and speed in ASIC designs
  • Understanding of complex issues related to timing closure, power integrity and signal integrity
  • Firm understanding of ASIC design flow including FET design, RTL, synthesis, timing, floorplanning
  • Experience with Cadence Innovus or equivalent toolset
  • Strong verbal, written communication, and presentation skills
  • Well organized, methodical, and detail oriented

Benefits For IP Integration Lead Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Mental Health Assistance
Parental Leave
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave and vacation time
  • Paid Family Leave
  • Annual discretionary bonus
  • Equity compensation

Interested in this job?

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