IP Integration Lead Engineer
Description For IP Integration Lead Engineer
Broadcom's ASIC Product Division (APD) is seeking an IP Integration Lead Engineer to join their team in Fort Collins, CO. This role is crucial in developing die-to-die PHY IP for custom silicon ASIC products. The position involves working with cutting-edge technology in physical composition and integration methodologies for complex 2.5D and 3DIC ASICs. The ideal candidate will be part of a cross-functional team, contributing to projects that span cloud computing AI engines, supercomputers, networking, and advanced wireless solutions. The role offers competitive compensation ($127,000 - $203,000) and comprehensive benefits including medical, dental, vision, 401(k) matching, and equity opportunities. This is an excellent opportunity for an experienced engineer to work with bleeding-edge intellectual property and contribute to developing products with sustainable competitive advantages. The position requires extensive experience in ASIC design flow and strong collaboration skills to work effectively across multiple teams.
Responsibilities For IP Integration Lead Engineer
- Develop a detailed understanding of Broadcom's die-to-die PHYs
- Work and coordinate with multiple cross functional teams to build PHYs
- Work with physical composition teams and interposer design teams to optimize signal IO patterns and escapes
- Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs
- Work with teams to analyze power integrity in various use cases and workloads
- Develop/write PHY integration documentation for ASIC composition teams
- Develop list of Checklist task for integration of PHY IP into ASICS
- Work with IP build teams to complete quality crosschecks
- Help support customer and ASIC PHY integration questions
Requirements For IP Integration Lead Engineer
- Bachelor's Degree in Electrical and Electronic Engineering or equivalent and 12+ years of related work experience or Masters degree and 10+ years of related experience
- Understanding of design trade offs for power, area, and speed in ASIC designs
- Understanding of complex issues related to timing closure, power integrity and signal integrity
- Firm understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC
- Experience with Cadence Innovus or equivalent toolset
- Strong verbal, written communication, and presentation skills
- Team player that can easily work with different personalities and skill levels
- Well organized, methodical, and detail oriented
Benefits For IP Integration Lead Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual bonus
- Equity awards
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