Layout Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Layout Engineer to join their team in Singapore. This role offers an exciting opportunity to work with cutting-edge technology in semiconductor design, focusing on layout engineering for various processes including advanced nodes like 16nm, 7nm, 5nm, and 3nm.

The position requires a strong background in layout engineering, with expertise in full custom and analog layout design. You'll be responsible for implementing complex layouts following strict guidelines for standard cells and I/O memories, while ensuring compliance with process rules and technical requirements. The role involves working with industry-standard tools like Cadence VIRTUOSO and CALIBRE verification tools.

As a Layout Engineer, you'll be involved in critical aspects of semiconductor design, including floor-planning, hierarchy layout, and chip integration. You'll need to demonstrate proficiency in physical verifications such as LVS, DRC, ERC, Antenna, and Electro Migration (EMIR) in CMOS process. Understanding of Latch-up and ESD in CMOS process is crucial for IO layout design.

For those taking on leadership responsibilities, the role extends to mentoring junior engineers, reviewing new technology design rules, and maintaining documentation for layout methodology and guidelines. The position offers growth opportunities and the chance to work with a global team at the forefront of semiconductor technology.

Broadcom provides a diverse and inclusive work environment, considering qualified applicants regardless of background. This role is perfect for someone who is passionate about semiconductor design, enjoys technical challenges, and wants to contribute to developing next-generation technology solutions.