Memory System Designer and Place and Route Engineer
Description For Memory System Designer and Place and Route Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Memory System Designer and Place and Route Engineer for their Mendota Heights location. This senior-level position combines hardware design expertise with software engineering skills, focusing on memory subsystem development.
The role requires 8 years of experience and offers a competitive salary range of $107,000 - $171,000, along with comprehensive benefits including medical coverage, 401(k) matching, and equity compensation. The position sits within the Central Engineering Group, where you'll be instrumental in developing large memory blocks and subsystems.
As a Memory System Designer, you'll be responsible for architecting and implementing memory subsystems, working with RTL designs, and managing physical design through place and route processes. The role demands expertise in various technical areas, from Verilog RTL coding to Python scripting, and requires proficiency with industry-standard tools for timing analysis, DRC, and EM/IR verification.
The ideal candidate will bring strong design skills, extensive experience with hardware description languages, and a deep understanding of memory systems. You'll need to demonstrate both technical excellence and leadership qualities, as the role involves complex problem-solving and cross-functional collaboration.
This position offers an opportunity to work on cutting-edge memory technologies at a leading semiconductor company, with the potential for professional growth and significant impact on product development. Broadcom's inclusive culture and comprehensive benefits package make this an attractive opportunity for experienced engineers looking to advance their careers in hardware design and memory systems.
Responsibilities For Memory System Designer and Place and Route Engineer
- Architect and design memory subsystems
- Implement RTL of subsystem designs
- Place and route (physical design)
- Design closure: timing, DRC, LVS, EM/IR, etc.
- Gate netlist synthesis
Requirements For Memory System Designer and Place and Route Engineer
- Bachelor in Electrical Engineering
- Minimum of 8 years of relevant experience
- Strong design skills
- Ability to write and debug Verilog RTL code
- Place and route expertise
- Proficient in running STA, DRC, EM/IR tools, and attaining design closure
- Ability to code in Python
- Good understanding of synthesis tools and running synthesis
- Capable of running and debugging logical equivalency checkers
- Familiar with memory behavior
- Proficient in writing automation scripts, and tools savvy
- Good communication, interpersonal, and leadership skills
- Motivated, self-driven, and good at multitasking
Benefits For Memory System Designer and Place and Route Engineer
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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