Physical Design Engineer

Broadcom Limited offers an excellent opportunity to contribute to a team environment and grow your personal career path. You will work with internal and external customers to develop state-of-the-art IC solutions using LSI's leading-edge CMOS cell-based ASIC technologies. Your responsibilities will cover all key development and implementation phases of ASIC designs, including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support.

Candidates will have the opportunity to work on the latest 16FF/7nm & 5nm designs. Detailed design tasks include:

1. Full Chip Synthesis and STA: Ideal candidates should have experience with full chip synthesis flow (DC, DCT, DCG) for 16nm/7nm design tape out, top design integration, and synthesis project experience. Experience running full chip STA and constraint clean-up flow is preferred.

2. Physical Design Implementation: Background in Physical Design, including floor planning, placement, design closure, and DRC & LVS skills.

Candidates are expected to develop most of these skills and should have a desire to seek in-depth and broad technical challenges.

Requirements:

• Good understanding of ASIC design flow and solid VLSI background
• Ability to handle block implementation/top-level tasks independently
• Tapeout experience in 28nm and below process design
• Strong communication and problem-solving skills
• Experience in DFT insertion, Synthesis & top integration, Power PDN/IVD analysis, or DRC/LVS is a plus
• Proficiency in Perl/Tcl/Python is beneficial

Education: MS degree preferred in Microelectronics or related discipline

Broadcom is an equal opportunity employer and considers qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other protected characteristic.