R&D Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
Embedded
Senior Software Engineer
In-Person
Enterprise SaaS

Description For R&D Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior R&D Engineer to join their TLR (top-level-route) team. This role focuses on advanced semiconductor design and verification, requiring expertise in physical design, verification, and integration of complex chip designs.

The position demands strong technical skills in Place and Route, CTS, and channel analysis, with emphasis on handling large-scale designs and understanding packaging requirements. You'll be responsible for crucial aspects of chip design, including physical verification, analog block integration, and implementing various fixes for signal integrity and noise.

The ideal candidate will possess deep knowledge of VLSI fabrication processes, calibre rule decks, and various industry-standard tools like Innovus and Calibre. Strong scripting abilities in Perl and TCL are essential for automation and efficiency. The role requires both technical expertise and excellent communication skills to collaborate effectively with team members.

This position offers an opportunity to work with cutting-edge semiconductor technology at a leading global company. You'll be part of a team that's pushing the boundaries of chip design and verification, working on complex projects that require both technical depth and breadth. The role provides exposure to the complete chip design cycle, from initial routing to final tape-out, making it an excellent opportunity for career growth in the semiconductor industry.

Last updated a month ago

Responsibilities For R&D Engineer

  • Place and Route, CTS, channel analysis with respect to routing and congestion
  • Handle big designs with understanding of packaging, bonding, and top-level requirements
  • Physical verification including DRC, LVS, Antenna, LUP (chip finishing and Tapeout)
  • Integration of analog blocks, meeting RC requirements for manual/special signals
  • Implementing ECOs, IR/IVD fixes, SPEF extraction, signal EM and Noise fixes
  • Responsible for integrity checks and post Tapeout eJob view release
  • Work closely with team members to accomplish PD milestone

Requirements For R&D Engineer

Python
  • Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup
  • Good scripting knowledge in perl and TCL
  • Familiarity with caliber, Innovus
  • Understanding of VLSI fabrication process
  • Good communication skills
  • Understanding of CTS, STA, PTSI and timing
  • Experience with CAD tools - cadence Innovus, Calibre

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