Staff Engineer - Memory Design Validation
Description For Staff Engineer - Memory Design Validation
Broadcom, a global technology leader in semiconductor and infrastructure software solutions, is seeking a Staff Engineer for Memory Design Validation. This role focuses on leading validation efforts for various memory types including SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers in cutting-edge 2nm process technologies. The position involves complex technical work including functional verification, signal integrity analysis, transistor-level simulations, and EM/IR analysis. The ideal candidate will have deep expertise in memory macro development, strong understanding of circuit behavior, and experience with industry-standard tools like Cadence, HSPICE, and various simulators. This role offers the opportunity to work on advanced semiconductor technologies and contribute to critical validation processes that ensure product quality and reliability. The position requires both technical excellence and leadership skills, as you'll be coordinating with various teams and leading validation initiatives.
Responsibilities For Staff Engineer - Memory Design Validation
- Lead Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers and custom macros
- Perform functional verification and resolve design discrepancies
- Conduct signal integrity analysis and propose solutions
- Perform transistor level simulations for Power Up and Lock up issues
- Conduct EM/IR analysis/simulations and evaluate timing impact
- Validate timing and internal margins through transistor level simulations
- Perform QA and validation checks for timing and power models
- Develop automation scripts for verification flow
- Support silicon debugging and correlation to spice models
- Coordinate with memory design leads on validation planning
Requirements For Staff Engineer - Memory Design Validation
- Strong expertise in memory macros development
- Strong understanding of transistor level circuit behavior and analysis
- Knowledge of layout challenges in sub-nanometer process technologies
- Understanding of signal integrity, EM/IR, and reliability analysis
- Knowledge of memory behavioral and physical models
- Understanding of DFT Schemes and chip level integration
- Proficiency in transistor level simulators and automation scripts
- Experience with Cadence schematic/layout editor tools
- Experience with HSPICE, HSIM, XA, FineSim, XARA, nWave tools
- Skill/Perl/Python Scripting experience
- Strong communication and leadership skills
- Problem solving and logical reasoning skills
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