Staff IP DFT Verification Engineer
Description For Staff IP DFT Verification Engineer
Broadcom's ASIC Product Division is seeking a Staff IP DFT Verification Engineer at their Bangalore Development Center. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies. The position involves working with cutting-edge semiconductor technology, particularly in the 3nm IP space and beyond.
The role combines technical expertise in DFT verification with collaborative teamwork across global teams. You'll be responsible for implementing and verifying DFT methodologies, working with advanced simulation tools, and ensuring quality standards for semiconductor products. The position requires interaction with customers and various engineering teams worldwide.
This is an excellent opportunity for experienced professionals who want to work at the forefront of semiconductor technology. The role offers exposure to advanced technologies like HBM, DDR, and SerDes IPs, while working with a global technology leader in the semiconductor industry. You'll be part of innovative solutions development and have the opportunity to influence future semiconductor testing methodologies.
The ideal candidate will bring strong technical expertise in DFT, excellent problem-solving abilities, and strong communication skills. This role provides the opportunity to work on complex technical challenges while contributing to the development of next-generation semiconductor solutions. Join Broadcom to be part of a team that's pushing the boundaries of semiconductor technology and testing methodologies.
Responsibilities For Staff IP DFT Verification Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for improvements
- Document verification processes and best practices
- Generate, verify & debug test vectors before tape release
- Validate & debug test vectors on ATE during silicon bring up
- Interface with customers, physical design and test teams globally
- Debug customer returned parts on the ATE
- Automate DFT & Test Vector Generation flows
Requirements For Staff IP DFT Verification Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting (Perl, Python, TCL, Ruby)
- Knowledge in analog and digital circuit design
- Excellent problem solving and debug skills
- Strong communication and teamwork abilities
- Bachelor's in Electrical/Electronic/Computer Engineering with 8+ years experience or Master's with 6+ years experience
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