STAFF IP DFT Verification Engineer
Description For STAFF IP DFT Verification Engineer
Broadcom's ASIC Product Division is seeking candidates for a STAFF IP DFT Verification Engineer position at their San Jose, California Development Center. The role involves ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies. Key responsibilities include implementing and verifying DFT methodologies, collaborating with cross-functional teams, utilizing advanced simulation tools, analyzing DFT-related data, documenting verification processes, and staying updated with the latest trends in DFT, HBM, and SerDes technologies.
The ideal candidate will have strong DFT background, experience in DFT verification (particularly with HBM, DDR, PCIE, and other SerDes IPs), understanding of DFT methodologies, proficiency in simulation tools and scripting languages, excellent analytical and problem-solving skills, and strong communication abilities. Additional skills such as experience with ATE, familiarity with BIST logic for array and link testing, and knowledge of AHB/APB/AXI buses are considered a plus.
Required qualifications include a Bachelor's degree in Electrical/Electronic/Computer Engineering with 8+ years of relevant industry experience, or a Master's degree in the same field with 6+ years of experience. The role offers an opportunity to work on cutting-edge technologies and contribute to innovative DFT solutions for 3nm IPs and beyond.
Broadcom is an equal opportunity employer and considers qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other protected characteristic.
Responsibilities For STAFF IP DFT Verification Engineer
- Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify and define critical testability requirements
- Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations
- Analyze DFT-related data and provide insights for continuous design improvements
- Document verification processes, results, and best practices to enhance team knowledge and efficiency
- Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team
- Work closely with STA and DI Engineers for test design closure
- Generate, verify & debug test vectors before tape release
- Validate & debug test vectors on ATE during the silicon bring up phase
- Assist with silicon failure analysis, diagnostics & yield improvement efforts
- Interface with customers, physical design and test engineering/manufacturing teams located globally
- Work closely with I/P DFT engineers & other stakeholders
- Debug customer returned parts on the ATE
- Innovate newer DFT solutions to solve testability problems in 3nm IPs & beyond
- Automate DFT & Test Vector Generation flows
Requirements For STAFF IP DFT Verification Engineer
- Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)
- Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs
- Understanding of DFT methodologies, including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby)
- Excellent analytical and problem-solving skills
- Strong communication and teamwork abilities
- Ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Excellent problem solving, debug, root cause analysis and communication skills
- Bachelor's in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Master's Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
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