Staff IP DFT Verification Engineer

Broadcom's ASIC Product Division is seeking candidates for a Staff IP DFT Verification Engineer position at their Bangalore Development Center. This role focuses on HBM/DDR/SERDES Verification and requires a highly skilled professional to ensure the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies.

Key Responsibilities:

• Implement and verify DFT methodologies for HBM, DDR, and SerDes designs
• Collaborate with design and architecture teams on testability requirements
• Utilize advanced simulation tools for DFT implementation verification
• Analyze DFT-related data and provide insights for design improvements
• Document verification processes and best practices
• Stay updated with latest trends in DFT, HBM, and SerDes
• Work on test vector generation, verification, and debugging
• Assist with silicon failure analysis and yield improvement
• Interface with global customers and teams
• Innovate DFT solutions for 3nm IPs and beyond
• Automate DFT and Test Vector Generation flows

Required Skills/Experience:

• Strong DFT background (Analog DFT, MBIST, IEEE1687)
• Experience in DFT verification, particularly with HBM, DDR, PCIE, and SerDes IPs
• Understanding of DFT methodologies (scan, BIST, ATPG)
• Proficiency in simulation tools and scripting (Perl, Python, TCL, Ruby)
• Excellent analytical, problem-solving, and communication skills
• Knowledge of analog and digital circuit design, and device physics
• Experience with ATE (preferred)
• Familiarity with BIST logic for array and link testing (preferred)
• Knowledge of AHB/APB/AXI buses (preferred)

Education:

• Bachelor's in Electrical/Electronic/Computer Engineering with 8+ years of experience, or
• Master's in Electrical/Electronic/Computer Engineering with 6+ years of experience

Broadcom is an equal opportunity employer and considers qualified applicants without discrimination based on protected characteristics.