ASIC Design for Test - Technical Lead

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Responsibilities:

• Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Develop innovative DFT IP in collaboration with multi-functional teams.
• Play a key role in full chip design integration with testability features coordinated in the RTL.
• Work closely with design/design-verification and PD teams to enable integration and validation of Test logic in all phases of implementation and post silicon validation flows.
• Participate in creating Innovative Hardware DFT & Test timing analysis for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

Minimum Qualifications:

• Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 7 years of experience.
• Experience with Jtag protocols (p1500, p1687), Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure.
• Experience with Gate level simulation, including timing based simulations with sdf, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
• Scripting skills: Tcl, Python/Perl.

Preferred Qualifications:

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development – Test Architecture, Methodology and Infrastructure

We offer competitive compensation, benefits, and opportunities for growth and innovation in a dynamic tech environment.