ASIC Design for Test - Technical Lead

The Common Hardware Group (CHG) at Cisco delivers silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As an ASIC Implementation Technical Lead focusing on Design-for-Test, you'll work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. You'll be part of the Silicon One development organization, crafting groundbreaking next-generation networking chips.

Key Responsibilities:

• Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics needs.
• Develop innovative DFT IP in collaboration with multi-functional teams.
• Integrate and validate Test logic in all phases of implementation and post-silicon validation flows.
• Create innovative Hardware DFT & Test timing analysis for new silicon device models.
• Craft solutions and debug with minimal mentorship.

Requirements:

• Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 7 years of experience.
• Experience with Jtag protocols, Scan and BIST architectures, ATPG and EDA tools.
• Expertise in Test static timing analysis constraints development and timing closure.
• Experience with Gate level simulation and debugging.
• Post-silicon validation and debug experience.
• Scripting skills: Tcl, Python/Perl.

Preferred Qualifications:

• Verilog design experience and familiarity with functional verification.
• DFT CAD development experience.

Cisco offers competitive compensation, including bonuses and equity, as well as comprehensive benefits including medical, dental, vision, 401(k), paid time off, and various wellbeing offerings.