ASIC Design for Test Technical Leader

The Common Hardware Group (CHG) at Cisco is seeking an ASIC Design for Test Technical Leader to join their Silicon One development organization in San Jose, CA. This role focuses on Design-for-Test, working with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.

As a member of this team, you'll be involved in crafting groundbreaking next-generation networking chips, leading the DFT and quality process through the entire Implementation flow and post-silicon validation phases. You'll also have exposure to physical design signoff activities.

Key responsibilities include:

• Implementing Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics needs.
• Developing innovative DFT IP in collaboration with multi-functional teams.
• Coordinating testability features in RTL and full chip design integration.
• Working closely with design/design-verification and PD teams to enable integration and validation of Test logic.
• Participating in creating innovative Hardware DFT & physical design aspects for new silicon device models.
• Crafting solutions and debugging with minimal mentorship.

The ideal candidate will have:

• Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 10 years of experience.
• Knowledge of the latest innovative trends in DFT, test, and silicon engineering.
• Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
• System Verilog Logic Equivalency checking and Test-timing validation skills.
• Experience with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience, including working with ATE patterns and P1687.
• Scripting skills in Tcl, Python/Perl.

Preferred qualifications include Verilog design experience, DFT CAD development, background in Test Static Timing Analysis, and past experience with post-silicon validation using DFT patterns.

Join Cisco and be part of a diverse, inclusive team that embraces digital transformation and innovation. Cisco offers competitive compensation, comprehensive benefits, and a culture that values work-life balance and giving back to the community.