Physical Design Engineer (Co-Op)

Cisco is seeking a Physical Design Engineer Co-op to join their elite optical communication products team. The co-op will be involved in various aspects of ASIC physical design and verification, working with cutting-edge submicron technologies.

Key responsibilities include:

• Collaborating with Front-End teams to understand design architecture for optimal physical implementation
• Performing gate level netlist synthesis (physical synthesis)
• Executing physical implementation (floorplanning, placement, CTS, routing)
• Optimizing power, performance, and area of designs
• Conducting Static Timing analysis and signoff closure
• Performing Physical verification and signoff closure
• Carrying out EMIR analysis and signoff closure

The ideal candidate should be:

• Currently enrolled in a full-time undergraduate program in computer science, electrical engineering, or a related field
• Able to work onsite in Maynard, MA two days a week
• Knowledgeable about the design cycle from RTL to GDSII
• Understanding of Static Timing Analysis, timing closure, and design constraints
• Familiar with block level synthesis, place and route, timing closure, PnR and signoff tools

Preferred qualifications include:

• Interest in VLSI design, specifically ASIC physical design and verification
• Academic experience in deep submicron CMOS technologies
• Scripting experience with perl, tcl, python, and/or shell
• Strong analytical and problem-solving skills
• Previous internship experience

Cisco offers a collaborative and inclusive work environment, with opportunities for professional growth and innovation. The company values diversity and encourages applicants from all backgrounds to apply.

Compensation: The salary range for this co-op position is $44,000 - $130,000 USD annually, not including equity or benefits. The actual compensation will be determined based on the candidate's qualifications, experience, and location.

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