CPU Design Engineer (Memsys/RISC-V/Out-of-Order cores)
Description For CPU Design Engineer (Memsys/RISC-V/Out-of-Order cores)
Join Codasip's CPU Design Team as a CPU Design Engineer, focusing on the recently launched Out-of-Order core project and memory subsystems. Collaborate with the IP team, working closely with Guillaume Bru from the French Design Center, Xubin Tan from the Barcelona Design Center, and CPU Architects based in the UK like Ben Fletcher and Tariq Kurd. You'll contribute to cutting-edge design projects, participate in next-generation architecture development, and work with Codasip's proprietary CodAL language.
Codasip is an innovative processor solutions company, designing and developing high-performance, energy-efficient CPU cores from scratch using proprietary tools for full customization. Based on the RISC-V open architecture, Codasip's Custom Compute approach utilizes the unique CodAL architecture description language and Codasip Studio for automated processor design.
This role offers the chance to work on complex projects, apply your ideas to processor architecture and design, and make a direct impact on the future of custom compute. You'll have autonomy to be creative with solutions and grow professionally in a dynamic environment that's disrupting the semiconductor industry.
Key responsibilities include:
- Developing Out-of-Order cores and memory subsystems
- Contributing to next-generation architecture development
- Working with CodAL language and Codasip Studio
- Collaborating with international teams across France, Spain, and the UK
- Optimizing designs for performance, power, and area (PPA)
- Utilizing hardware description languages, particularly Verilog/SystemVerilog
- Implementing and optimizing multicore cache coherence systems
- Working with versioning tools and scripting languages in a Linux environment
Join Codasip to be part of the custom compute revolution and help build innovative RISC-V processor solutions that give customers a unique competitive advantage in system-on-chip development.
Responsibilities For CPU Design Engineer (Memsys/RISC-V/Out-of-Order cores)
- Collaborate with the IP team on Out-of-Order core projects and memory subsystems
- Contribute to cutting-edge design projects and next-generation architectures
- Work with Codasip's proprietary CodAL language
- Design and optimize CPU cores for performance, power, and area
- Implement and improve multicore cache coherence systems
- Utilize hardware description languages for CPU design
- Participate in the development of RISC-V based processor solutions
- Work on automated processor design using Codasip Studio
Requirements For CPU Design Engineer (Memsys/RISC-V/Out-of-Order cores)
- Good knowledge of modern CPU architectures (ideally RISC-V) and micro-architectures, or track record in complex pipelined designs
- Hands-on experience with at least one Hardware Description Language (preferably Verilog/SystemVerilog)
- Good knowledge of Out-of-Order core development and multicore cache coherence
- Understanding of the CHI protocol
- Sharp understanding of physical implications when designing at a higher level of abstraction
- Skills to design and optimize a module around a given PPA point
- Practical expertise in versioning tools (preferably git)
- Proficiency in scripting languages (Shell, Python, Tcl)
- Practical usage of Linux
- Proficiency in digital design synthesis and implementation flow
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