Principal UVM Verification Engineer
Description For Principal UVM Verification Engineer
Fabric Cryptography is an innovative Series A deep tech company with a team of 60+ professionals, including AI hardware and software veterans, cryptographers, and cypherpunks. The company is focused on developing the Verifiable Processing Unit (VPU), a groundbreaking general-purpose computer chip designed for all cryptography applications. With $39 million in equity funding and significant pre-orders, they're revolutionizing privacy-first computing.
As a Principal UVM Verification Engineer, you'll play a crucial role in ensuring the quality and reliability of their cryptographic processor designs. The position requires a deep understanding of hardware verification, SoC development, and modern verification methodologies. You'll work with cutting-edge technology in cryptography and hardware design, contributing to the development of next-generation privacy-focused computing solutions.
The role offers the opportunity to work with a highly skilled team of professionals and make significant contributions to the architecture and methodology of the verification environment. You'll be responsible for developing comprehensive verification strategies, implementing sophisticated testbenches, and ensuring the highest standards of quality in hardware design.
This position is ideal for an experienced verification engineer who is passionate about cryptography, hardware design, and privacy-focused technology. The remote work option and presence in major tech hubs across the US provide flexibility while maintaining strong team collaboration. If you're excited about working at the intersection of hardware and cryptography, and want to be part of a company that's shaping the future of privacy-first computing, this role offers an exceptional opportunity to make a significant impact.
Responsibilities For Principal UVM Verification Engineer
- Work on verification of a proprietary cryptographic processor and SoC
- Contribute to the architecture and methodology of DV environment and team from scratch
- Develop and execute verification plans and testbenches
- Write and maintain directed and constrained random tests
- Work cross functionally to integrate verification environment into overall design flow
- Own and develop formal and UVM verification methods
- Provide technical guidance to team members
Requirements For Principal UVM Verification Engineer
- BS, MS, PhD in Electrical Engineering, Computer Science, or related field
- 10+ years of strong experience with design verification
- Integration of third-party IP into an SoC
- Experience with an SoC through tapeout and post-silicon
- Knowledge of CDC, XProp, and DFT
- UVM testbench development from scratch, SystemC/C++ experience a plus
- Python knowledge and scripting/automating DV flows
- Good understanding of digital design, including RTL design, UVM, System Verilog and synthesis
- Knowledge of cryptography and data protection is a plus
- Excellent written and verbal communication skills
- Ability to work independently, under pressure and in a startup setting
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