AI/ML RTL Design Engineer, TPU, Google Cloud
Description For AI/ML RTL Design Engineer, TPU, Google Cloud
Google is seeking an AI/ML RTL Design Engineer to join their TPU (Tensor Processing Unit) team in Bengaluru. This role is crucial in shaping the future of AI/ML hardware acceleration, working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. The position involves developing System-on-a-chip (SoC) solutions used to accelerate machine learning computation in data centers.
As part of the Technical Infrastructure team, you'll be responsible for implementing AI/ML compute-intensive IPs and subsystems, managing RTL implementation, and working on design methodology. The role requires expertise in ASIC/SoC development, machine learning hardware design, and verification processes. You'll collaborate with various teams including architecture, verification, power and performance, and physical design to deliver high-quality solutions for next-generation data center accelerators.
The ideal candidate will have strong experience in hardware design, particularly with Verilog/SystemVerilog, and a solid understanding of machine learning architectures. You'll be working with a diverse team that pushes boundaries and develops custom silicon solutions that power Google's TPU infrastructure. This is an excellent opportunity for someone passionate about hardware design and AI/ML technologies to make a significant impact on Google's infrastructure.
The position offers the chance to work on innovative products used by millions worldwide, contributing to Google's cutting-edge AI/ML hardware acceleration capabilities. You'll be part of a team that's proud to be "engineers' engineers" and focuses on building and maintaining the architecture that keeps Google's product portfolio running efficiently.
Responsibilities For AI/ML RTL Design Engineer, TPU, Google Cloud
- Participate in implementation of AI/ML Compute intensive IPs and subsystems
- Take ownership of Register-Transfer Level (RTL) implementation and quality checks of one or more modules
- Contribute to design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams
- Identify and drive power, performance and area improvements for the modules owned
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
Requirements For AI/ML RTL Design Engineer, TPU, Google Cloud
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience
- 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog
- Experience in design of Machine Learning IPs, or graphics IPs, managing low precision/mixed precision numerics
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience with programming languages (Python, C/C++ or Perl)
- Knowledge of high performance and low power design techniques
- Knowledge of neural networks, arithmetic units, processor design, accelerators, bus architectures or memory hierarchies
Benefits For AI/ML RTL Design Engineer, TPU, Google Cloud
- Equal opportunity employer
- Accommodation for special needs
- Global collaboration opportunities
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