Application-specific integrated circuit (ASIC) Design Verification Engineer
Description For Application-specific integrated circuit (ASIC) Design Verification Engineer
Google is seeking an ASIC Design Verification Engineer to join their hardware team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with software development, working on next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. The position requires strong verification skills using SystemVerilog and UVM, along with experience in digital systems and standard IP components.
The role involves working with cutting-edge technology that powers Google's hardware experiences, requiring expertise in design verification, RTL-level verification, and various verification methodologies. You'll be part of a diverse team that pushes boundaries in hardware development, contributing to products used by millions worldwide.
Key responsibilities include planning and executing verification of complex systems, creating verification environments, developing cross-language tools, and working closely with design engineers to ensure product quality. The ideal candidate will have a strong background in electrical engineering or computer science, with experience in verification methodologies and digital systems.
This position offers the opportunity to work on innovative hardware solutions at one of the world's leading technology companies, contributing to the future of Google's hardware ecosystem. You'll be part of a team that combines AI, software, and hardware expertise to create radically helpful experiences, making computing faster, seamless, and more powerful.
Responsibilities For Application-specific integrated circuit (ASIC) Design Verification Engineer
- Plan and execute the verification of the next generation configurable Infrastructure Internet protocols (IPs), interconnects and memory subsystems
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Develop cross language tools and scalable verification methodologies
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct blocks and subsystems
Requirements For Application-specific integrated circuit (ASIC) Design Verification Engineer
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience in Design Verification, verifying digital reasoning at RTL level using C/C++, SystemVerilog or UVM
- Experience in verifying digital systems using standard IP components/interconnects
- Experience in creating and using verification components and environments in standard verification methodology
- Experience in coding languages and software development frameworks
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