ASIC Design Engineer

Google organizes world's information and makes it universally accessible and useful, combining AI, Software, and Hardware.
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Entry-Level Software Engineer
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3+ years of experience
AI · Consumer · Hardware

Description For ASIC Design Engineer

Google is seeking an ASIC Design Engineer to join their hardware team, focusing on developing custom silicon solutions for direct-to-consumer products. This role is perfect for engineers passionate about hardware design and innovation, as you'll be working on products used by millions worldwide. The position involves RTL development, debug simulations, and quality checks, requiring expertise in ASIC methodology and ARM-based SoCs.

The role combines technical expertise in hardware design with the opportunity to work on cutting-edge technology at one of the world's leading tech companies. You'll be part of a diverse team pushing boundaries in custom silicon development, directly impacting Google's consumer products. The position requires strong skills in Verilog/System Verilog and microarchitecture, along with experience in scripting languages like Python or Perl.

Working at Google means you'll be at the forefront of combining AI, software, and hardware to create revolutionary computing experiences. The team's mission is to make technology more helpful and accessible to people worldwide. You'll collaborate with multi-disciplined teams across different locations, contributing to various aspects of the development process from RTL development to silicon bring-up.

This is an excellent opportunity for someone who wants to impact the future of hardware experiences while working with state-of-the-art technology and a talented team. The role offers the chance to work on projects that require both technical depth and creative problem-solving, all while contributing to Google's mission of organizing the world's information and making it universally accessible and useful.

Last updated a day ago

Responsibilities For ASIC Design Engineer

  • Perform RTL development (SystemVerilog), and debug functional/performance simulations
  • Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
  • Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
  • Communicate and work with multi-disciplined and multi-site teams

Requirements For ASIC Design Engineer

Python
  • Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience
  • Experience with ARM-based SoCs, interconnects, and ASIC methodology
  • Experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with a scripting language like Python or Perl
  • Master's degree in Electrical or Computer Engineering (preferred)
  • 3 years of experience with IP design for clocking, interconnects, and peripherals (preferred)
  • Experience with methodologies for low power estimation, timing closure, and synthesis (preferred)
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC) (preferred)

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