ASIC Design Engineer, Silicon
Description For ASIC Design Engineer, Silicon
Google is seeking an ASIC Design Engineer to join their hardware team working on custom silicon solutions for direct-to-consumer products. This role focuses on designing foundation and chassis IPs for Pixel System on Chips (SoCs), including Network on Chip, Clock, Debug, IPC, and Memory Management Unit components. The position requires extensive experience in ARM-based SoCs, RTL design, and ASIC methodology.
As part of Google's mission to organize world information and make it universally accessible, you'll work with a diverse team that combines the best of Google AI, Software, and Hardware to create innovative experiences. The role involves collaborating with various teams including architecture, software, verification, power, and timing to deliver high-quality RTL implementations.
The ideal candidate will have strong technical skills in microarchitecture and low power design methodology, with the ability to evaluate design options considering performance, power, and area constraints. You'll be responsible for developing RTL implementations, participating in various stages of the design process from test planning to silicon bring-up, and creating automation tools to improve efficiency.
This position offers the opportunity to contribute to products used by millions worldwide, working at the forefront of hardware innovation. You'll be part of Google's commitment to creating radically helpful experiences through technology, with the chance to shape the next generation of hardware solutions. The role combines technical expertise with collaborative teamwork, making it ideal for engineers passionate about pushing the boundaries of silicon design.
Responsibilities For ASIC Design Engineer, Silicon
- Participate in test planning and coverage analysis
- Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For ASIC Design Engineer, Silicon
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
- Master's degree or PhD in Electrical Engineering, Computer Science preferred
- 6 years of industry experience with Intellectual Property (IP) design preferred
- Experience with methodologies for RTL quality checks preferred
- Experience with methodologies for low power estimation, timing closure, synthesis preferred
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