ASIC Design Engineer, Silicon
Description For ASIC Design Engineer, Silicon
Google is seeking an ASIC Design Engineer to join their hardware team focusing on custom silicon solutions for direct-to-consumer products. This role involves designing foundation and chassis IPs for Pixel System on Chips, including Network on Chip, Clock, Debug, IPC, and Memory Management Unit components. The position requires extensive experience with ARM-based SoCs, RTL design, and ASIC methodology.
The ideal candidate will collaborate across multiple teams including architecture, software, verification, power, and timing to deliver high-quality RTL implementations. They will be responsible for solving technical challenges related to micro-architecture and low power design methodology, while considering performance, power, and area optimization.
This opportunity offers the chance to work on Google's next generation of hardware experiences, contributing to products used by millions worldwide. The role combines technical expertise in hardware design with the innovation and scale of Google's ecosystem. The team's mission is to create radically helpful experiences by combining Google's strengths in AI, software, and hardware.
The position requires strong technical skills in Verilog/SystemVerilog, experience with RTL design, and familiarity with various methodologies for quality checks and power estimation. The successful candidate will participate in all aspects of the design process, from test planning to silicon bring-up, while also creating automation tools to improve efficiency.
Working at Google provides the opportunity to impact millions of users while being part of a diverse team that pushes boundaries in hardware innovation. The role offers exposure to cutting-edge technology and the chance to shape the future of Google's hardware products.
Responsibilities For ASIC Design Engineer, Silicon
- Participate in test planning and coverage analysis
- Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For ASIC Design Engineer, Silicon
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience (preferred)
- 6 years of industry experience with Intellectual Property (IP) design (preferred)
- Experience with methodologies for Register-Transfer Level (RTL) quality checks (preferred)
- Experience with methodologies for low power estimation, timing closure, synthesis (preferred)
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