ASIC Design Engineer, Silicon
Description For ASIC Design Engineer, Silicon
Google is seeking an experienced ASIC Design Engineer to join their Silicon team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role involves designing foundation and chassis IPs for Pixel System on Chips (SoCs), including Network on Chip, Clock, Debug, IPC, and Memory Management Unit components. The position requires deep expertise in ARM-based SoCs, RTL design, and ASIC methodology.
The ideal candidate will collaborate with cross-functional teams in architecture, software, verification, power, and timing to deliver high-quality RTL implementations. They will be responsible for solving technical challenges related to micro-architecture and low power design methodology, while optimizing for performance, power, and area considerations.
This role is part of Google's broader mission to create radically helpful experiences by combining AI, Software, and Hardware expertise. The team focuses on developing new technologies to make computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology.
The position offers the opportunity to work on cutting-edge hardware projects that impact millions of users worldwide. Located in Bengaluru, India, this role requires strong technical skills in Verilog/SystemVerilog, RTL design, and experience with Python or Perl for automation tasks. The successful candidate will contribute to all aspects of the design process, from initial planning through to silicon bring-up.
Responsibilities For ASIC Design Engineer, Silicon
- Participate in test planning and coverage analysis
- Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For ASIC Design Engineer, Silicon
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
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