ASIC Design For Testability Engineer, Silicon
Description For ASIC Design For Testability Engineer, Silicon
Google is seeking an experienced ASIC Design For Testability Engineer to join their hardware team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position involves working with cutting-edge technology and contributing to products used by millions worldwide.
As an ASIC DFT Engineer, you'll be part of a diverse team that pushes boundaries in hardware development. You'll work closely with DFT engineers, RTL, and Physical Designer Engineers to implement complex testing solutions for ASIC designs. The role requires expertise in ATPG, Low Power designs, BIST, JTAG, and IJTAG tools and flows.
The ideal candidate should have strong experience with DFT EDA tools, particularly Tessent, and be proficient in developing automated workflows using Python and Tcl. You'll be responsible for working on subsystem level DFT SCAN and MBIST Architecture with multiple voltage and power domains.
At Google, you'll have the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The company's mission focuses on organizing world's information and making it universally accessible through the combination of AI, Software, and Hardware technologies.
This position offers the chance to work on innovative projects that directly impact Google's hardware products while collaborating with world-class engineers. The role requires both technical expertise and the ability to work effectively in a team environment, making it an excellent opportunity for someone passionate about hardware design and testing.
Responsibilities For ASIC Design For Testability Engineer, Silicon
- Work with a team of DFT engineers, RTL and Physical Designer Engineers
- Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains
- Write scripts to automate the DFT flow
- Develop tests that can be used for Production in the ATE flow
Requirements For ASIC Design For Testability Engineer, Silicon
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience
- 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing
- Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow
- Experience with DFT EDA tools (e.g., Tessent)
- Experience with DFT for subsystems with multiple physical partitions
- Experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent tool
- Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths
- Experience in developing automated workflows using Python and Tcl
- Experience in collaborating with Design, PD, and STA teams
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