ASIC Design for Testability Engineer, Silicon
Description For ASIC Design for Testability Engineer, Silicon
Google is seeking an ASIC Design for Testability Engineer to join their hardware team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As part of a diverse team, you'll be working on cutting-edge hardware development, focusing on Design for Testability (DFT) implementation and optimization.
The position requires extensive experience in ASIC design for test, including work with silicon life cycle, DFT pattern bring-up on ATE, and manufacturing. You'll be responsible for implementing and managing complex DFT architectures, working with multiple voltage and power domains, and developing automated testing solutions.
The ideal candidate will have strong expertise in ATPG, BIST, JTAG, and various DFT EDA tools. You'll need to demonstrate proficiency in scripting languages and have a deep understanding of SOC design flows. The role offers the opportunity to work with multi-disciplined teams across different locations, contributing to products that impact millions of users worldwide.
This position at Google combines the challenge of complex hardware development with the excitement of working on next-generation consumer products. You'll be part of a team that pushes boundaries in silicon development, focusing on performance, efficiency, and integration. The role offers the chance to work with cutting-edge technology while contributing to Google's mission of organizing the world's information and making it universally accessible.
If you're passionate about hardware development, have strong technical skills in ASIC design and testing, and want to be part of creating innovative solutions that power Google's future products, this role presents an excellent opportunity to make a significant impact in a dynamic, collaborative environment.
Responsibilities For ASIC Design for Testability Engineer, Silicon
- Work with a team of DFT engineers, working with RTL and Physical Designer Engineers
- Work on Subsystem level DFT SCAN, Memory Built-In Self-Test (MBIST) Architecture with multiple voltage, power domains
- Write basic to complex scripts to automate the DFT flow
- Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC Design for Testability Engineer, Silicon
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience
- 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing
- Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow
- Experience with DFT EDA tools (e.g., Tessent)
- Experience with scripting languages such as Perl or Python
- Experience in DFT for a Complex subsystem with multiple physical partitions
- Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG
- Understanding of the flows - Design, Verification, DFT and PD Phases in a SOC cycle
- Ability to scale DFT, with a focus on minimal area overhead
