ASIC Design Verification Associate Engineer, Devices and Services
Description For ASIC Design Verification Associate Engineer, Devices and Services
Google is seeking an ASIC Design Verification Associate Engineer to join their Devices and Services team. This role focuses on developing and verifying custom silicon solutions that power Google's direct-to-consumer products. The position involves working on System on a Chip (SOC) verification, collaborating with hardware architects and design engineers for functional and performance verification of infrastructure IP, interconnects, caches, memory management, and system services.
The ideal candidate will have a strong background in electrical engineering or computer science, with experience in digital system verification, SystemVerilog, and various hardware verification methodologies. They will be responsible for creating and enhancing verification environments, developing cross-language tools, and ensuring the quality of hardware components through thorough testing and debugging.
This is an excellent opportunity to work on cutting-edge hardware technology at one of the world's leading tech companies. The role offers the chance to contribute to products used by millions of people worldwide, working with state-of-the-art tools and methodologies in hardware verification. The position combines technical depth in hardware verification with the excitement of working on consumer-facing products that make a real impact.
The team's mission is to create radically helpful experiences by combining Google's expertise in AI, software, and hardware. You'll be part of a dynamic environment that values innovation and technical excellence, with opportunities to work on next-generation hardware solutions that push the boundaries of what's possible in computing technology.
Responsibilities For ASIC Design Verification Associate Engineer, Devices and Services
- Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Develop cross language tools and scalable verification methodologies
- Identify and write types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct blocks and subsystems
Requirements For ASIC Design Verification Associate Engineer, Devices and Services
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- Experience in verifying digital systems using standard IP components/interconnects
- Experience with Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, Python
- Experience in creating and using verification components and environments in standard verification methodology
- Experience with scripting languages and Software development frameworks
- Experience in verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or C/C++
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