ASIC Design Verification Engineer
Description For ASIC Design Verification Engineer
Google is seeking an ASIC Design Verification Engineer to join their Technical Infrastructure team, focusing on shaping the future of AI/ML hardware acceleration. This role offers an exciting opportunity to work on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. The position involves developing custom silicon solutions that drive the future of Google's TPU infrastructure.
As part of this role, you'll be responsible for verifying complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You'll work alongside talented engineers to develop ASICs used to accelerate computation in data centers, with responsibilities spanning project definition, design verification, and silicon bringup.
The Technical Infrastructure team is crucial in maintaining Google's vast architecture, from developing and maintaining data centers to building next-generation Google platforms. The team takes pride in being the "engineers' engineers" and ensures networks run optimally for the best user experience.
This position offers a competitive compensation package, including a base salary range of $113,000-$161,000, plus bonus, equity, and comprehensive benefits. The role requires strong technical skills in SystemVerilog, UVM testbenches, and verification methodologies. You'll be working with cutting-edge technology while contributing to products used by millions worldwide.
The ideal candidate should have at least a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, with 1 year of design verification experience. Strong problem-solving abilities, experience with coverage analysis tools, and excellent debugging skills are essential for success in this role.
Join Google's team and be part of developing the next generation of data center accelerators, working on projects that push the boundaries of technology and innovation. This role offers the perfect blend of technical challenge and real-world impact, making it an excellent opportunity for someone passionate about hardware verification and AI/ML technology.
Responsibilities For ASIC Design Verification Engineer
- Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For ASIC Design Verification Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience in design verification
- Experience with UVM testbenches and methodologies (preferred)
- Experience developing and executing test plans (preferred)
- Proficient in SystemVerilog, including object-oriented programming, SVAs and functional coverage (preferred)
- Familiarity with coverage analysis tools (e.g., Verdi, Questa) (preferred)
- Excellent problem-solving and debugging skills (preferred)
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