ASIC Design Verification Engineer

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Mid-Level Software Engineer
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5,000+ Employees
3+ years of experience
AI · Consumer · Enterprise SaaS

Description For ASIC Design Verification Engineer

Google is seeking an ASIC Design Verification Engineer to join their hardware team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with Google's innovative approach to technology, working on products that impact millions of users worldwide.

The position requires strong expertise in formal verification, with a focus on digital logic verification at the RTL level using SystemVerilog. You'll be working with cutting-edge verification tools and methodologies, contributing to the development of next-generation hardware experiences that deliver exceptional performance and efficiency.

As an ASIC Design Verification Engineer, you'll be responsible for planning and implementing verification strategies, creating properties and constraints for digital design blocks, and utilizing advanced formal verification tools. The role demands both technical depth in hardware verification and the ability to contribute to methodology improvements.

The ideal candidate will have a strong background in Electrical Engineering or Computer Science, with specific expertise in formal verification domains. Experience with tools like JasperGold, VC Formal, or Questa Formal is highly valued, as is knowledge of formal methodology and abstraction techniques.

This is an opportunity to work with a diverse team at Google, contributing to innovative hardware solutions that power popular consumer products. You'll be part of a company that values technical excellence, creativity, and the ability to impact users' lives through technology. The role offers the chance to work on challenging problems at scale, with access to Google's vast resources and expertise in AI, software, and hardware integration.

Last updated 3 months ago

Responsibilities For ASIC Design Verification Engineer

  • Plan the formal verification strategy and create the properties/constraints for digital design blocks
  • Utilize formal property verification tools combined with formal verification closure techniques to verify properties
  • Contribute improvements to methodologies to enhance formal verification results
  • Architect and implement reusable formal verification components

Requirements For ASIC Design Verification Engineer

Python
  • Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience
  • 3 years of experience in the formal verification domain
  • Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level
  • Experience with scripting languages (e.g., Python/Perl, and TCL)
  • Experience in formal verification applications and data-path verification
  • Experience with formal sign-offs of industry ASIC designs
  • Knowledge of formal methodology and formal abstraction techniques

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