ASIC Design Verification Engineer, Devices and Services

Google organizes the world's information to make it universally accessible and useful, combining AI, Software, and Hardware innovation.
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Hardware

Description For ASIC Design Verification Engineer, Devices and Services

Google is seeking an ASIC Design Verification Engineer to join their Devices and Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with cutting-edge technology to create next-generation hardware experiences. The position requires strong verification skills in digital logic, SystemVerilog, and experience with standard IP components.

As an ASIC Design Verification Engineer, you'll be responsible for planning and executing verification of infrastructure IPs, working with advanced interconnects and memory subsystems. The role demands expertise in constrained-random verification environments and cross-language tools development. You'll collaborate with design engineers to ensure functional correctness and maintain high verification standards.

The ideal candidate should have at least 3 years of experience in digital logic verification at the RTL level, with a strong background in SystemVerilog or C/C++. Knowledge of standard verification methodologies and IP components is essential. The position offers the opportunity to work on products that impact millions of users worldwide, combining Google's strengths in AI, software, and hardware.

This role is perfect for someone who wants to be at the forefront of hardware innovation, working with cutting-edge technology in a company that values diversity and inclusion. You'll be part of a team that pushes boundaries in custom silicon development, directly contributing to the future of Google's consumer products.

Last updated 4 days ago

Responsibilities For ASIC Design Verification Engineer, Devices and Services

  • Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM
  • Develop cross language tools and verification methodologies
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct blocks and subsystems and close coverage measures

Requirements For ASIC Design Verification Engineer, Devices and Services

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 3 years of experience verifying digital logic at RTL level using SystemVerilog or C/C++
  • Experience creating and using verification components and environments in standard verification methodology
  • Experience verifying digital systems using standard IP components/interconnects
  • Experience with scripting languages and software development frameworks

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