ASIC Design Verification Engineer, Machine Learning, Early Career
Description For ASIC Design Verification Engineer, Machine Learning, Early Career
Google is seeking an ASIC Design Verification Engineer to join their Technical Infrastructure team, focusing on Machine Learning hardware development. This role is crucial in developing and verifying complex digital designs that power Google's cutting-edge data centers and services.
As an ASIC Design Verification Engineer, you'll be at the forefront of Google's custom hardware development, working on systems that form the backbone of the world's most powerful computing infrastructure. Your responsibilities will span from verification planning to test execution and coverage closure, using SystemVerilog and UVM to build efficient verification environments.
The role offers a unique opportunity to work on hardware that directly impacts millions of Google users. You'll collaborate closely with design engineers, verify complex digital blocks, and ensure the quality of Google's custom ASIC designs. The position requires strong skills in SystemVerilog and digital logic verification, with opportunities to work on cutting-edge machine learning hardware.
The compensation package is competitive, ranging from $108,000 to $158,000 base salary, plus bonus, equity, and comprehensive benefits. Google offers a collaborative environment where you'll work with talented engineers and have access to state-of-the-art resources and technologies.
This is an excellent opportunity for early-career professionals with a background in Electrical or Computer Engineering to join a company at the forefront of technology innovation. You'll gain invaluable experience in hardware verification while contributing to projects that power Google's diverse portfolio of products and services.
The role combines technical depth with collaborative teamwork, requiring both strong verification skills and excellent communication abilities. You'll be part of a team that takes pride in building the architecture behind everything users see online, making this an ideal position for someone passionate about hardware engineering and verification.
Responsibilities For ASIC Design Verification Engineer, Machine Learning, Early Career
- Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For ASIC Design Verification Engineer, Machine Learning, Early Career
- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience
- 1 year of experience coding in SystemVerilog through internships or work experience
- Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs
- Experience with verification methodology such as UVM/OVM/VMM (preferred)
- Experience with the full verification life cycle (preferred)
- Experience in SystemVerilog (preferred)
- Excellent team player, problem-solving, and communication skills (preferred)
