ASIC Design Verification Engineer, TPU Compute

A leading technology company that designs and develops innovative hardware, software, and AI solutions.
$132,000 - $189,000
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
AI

Description For ASIC Design Verification Engineer, TPU Compute

Google is seeking an ASIC Design Verification Engineer to join their TPU (Tensor Processing Unit) Compute team in Sunnyvale, CA. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for designing and implementing hardware and software infrastructure for Google services and Google Cloud.

The position offers an exciting opportunity to shape the future of AI/ML hardware acceleration by working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. As part of the team, you'll be developing custom silicon solutions and verifying complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Key responsibilities include planning verification of digital design blocks, creating verification environments using SystemVerilog and UVM, debugging tests with design engineers, and ensuring comprehensive coverage for tape-out readiness. The role requires strong technical expertise in ASIC design verification and familiarity with industry-standard tools and methodologies.

The compensation package is competitive, ranging from $132,000 to $189,000 base salary, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone with a background in Computer Science or Electrical Engineering who wants to work at the forefront of AI hardware development.

The position offers growth potential within Google's innovative environment, working alongside talented engineers and contributing to technology that impacts billions of users. The role combines technical depth in hardware verification with the excitement of developing next-generation AI accelerators, making it an ideal opportunity for someone passionate about both hardware development and artificial intelligence.

Working at Google's Sunnyvale location, you'll be part of a global team that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. The role offers the chance to work on projects with significant impact, from developing TPUs to supporting Google Cloud's Vertex AI platform, which brings Gemini models to enterprise customers.

Last updated 2 hours ago

Responsibilities For ASIC Design Verification Engineer, TPU Compute

  • Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
  • Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver correct design blocks
  • Close coverage measures to identify verification holes and to show progress towards tape-out

Requirements For ASIC Design Verification Engineer, TPU Compute

  • Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience
  • 2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips
  • Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage)

Benefits For ASIC Design Verification Engineer, TPU Compute

Medical Insurance
Equity
401k
  • Medical Insurance
  • Equity
  • 401k

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