ASIC Design Verification Engineer, TPU Compute
Description For ASIC Design Verification Engineer, TPU Compute
Google is seeking an ASIC Design Verification Engineer to join their TPU (Tensor Processing Unit) team, focusing on shaping the future of AI/ML hardware acceleration. This role offers an opportunity to drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications. As part of a diverse team, you'll develop custom silicon solutions for Google's TPU, contributing to products used by millions worldwide.
The position involves working on ASICs used to accelerate computation in data centers, with responsibilities spanning project definition, design verification, and silicon bringup. You'll participate in the architecture, documentation, and verification of next-generation data center accelerators. The role requires expertise in SystemVerilog and verification methodologies, with a focus on creating comprehensive verification environments and ensuring thorough coverage of complex digital designs.
Behind the scenes, you'll be part of the Technical Infrastructure team that maintains Google's architecture, from developing data centers to building next-generation Google platforms. The team takes pride in being the engineers' engineers, ensuring networks run optimally for the best user experience. This role offers competitive compensation, including base salary, bonus, equity, and comprehensive benefits.
The ideal candidate will have strong experience in design verification, familiarity with industry-standard tools, and the ability to work effectively with design engineers. This is an excellent opportunity for someone passionate about hardware verification and interested in working at the forefront of AI/ML technology development.
Responsibilities For ASIC Design Verification Engineer, TPU Compute
- Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For ASIC Design Verification Engineer, TPU Compute
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience
- 3 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage)
Benefits For ASIC Design Verification Engineer, TPU Compute
- Medical Insurance
- Equity
- 401k
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