ASIC DFT Engineer, Silicon

Google is seeking an ASIC DFT Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware engineering with software development, requiring expertise in DFT (Design for Testability) methodologies and automation.

The position offers an opportunity to work on cutting-edge hardware development that powers Google's consumer products, directly impacting millions of users worldwide. As part of the team, you'll collaborate with RTL and Physical Designer Engineers to implement sophisticated testing architectures and automated workflows.

The ideal candidate should have a strong foundation in electrical engineering or computer science, with specific expertise in DFT flows and methodology. Experience with Python and TCL scripting is essential, as you'll be responsible for developing and maintaining automated testing frameworks.

Key responsibilities include designing subsystem level DFT SCAN and MBIST Architecture across multiple voltage and power domains, creating automated DFT flows, and developing production-ready tests for ATE flow. This role is perfect for someone who combines hardware expertise with software automation skills.

Google offers a collaborative environment where you'll work with diverse teams pushing the boundaries of hardware innovation. The position is based in Bengaluru, India, and is part of Google's broader mission to create radically helpful experiences for users through the combination of AI, Software, and Hardware.

This role presents an excellent opportunity for growth within Google's hardware division, allowing you to contribute to next-generation technology while working with state-of-the-art tools and methodologies. You'll be at the forefront of developing testing solutions that ensure the quality and reliability of Google's hardware products.