ASIC RTL Engineer, Silicon

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Consumer

Description For ASIC RTL Engineer, Silicon

Google is seeking an ASIC RTL Engineer to join their hardware team, focusing on developing custom silicon solutions for direct-to-consumer products. This role combines hardware engineering expertise with Google's innovative approach to product development. The position requires strong experience in digital logic design and RTL concepts, with a focus on optimization and low-power design techniques.

As an ASIC RTL Engineer, you'll be instrumental in shaping the next generation of hardware experiences at Google. You'll work on projects that directly impact millions of users worldwide, contributing to the development of high-performance, efficient silicon solutions. The role involves collaboration with multi-disciplinary teams across different locations, participating in various stages of the design process from documentation to silicon bring-up.

The ideal candidate should have a strong foundation in electrical or computer engineering, with specific expertise in RTL design and verification. Knowledge of scripting languages like Python and experience with ASIC/FPGA design verification are valuable assets. You'll be working in an environment that values diversity and innovation, with access to cutting-edge technology and resources.

This position offers the opportunity to work on challenging projects that push the boundaries of hardware development, while being part of Google's mission to organize world's information and make it universally accessible. You'll contribute to products that combine the best of Google's AI, software, and hardware capabilities, making computing faster, seamless, and more powerful for users worldwide.

Last updated 3 hours ago

Responsibilities For ASIC RTL Engineer, Silicon

  • Define the block level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.)
  • Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks
  • Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
  • Participate in test plan and coverage analysis of the block and ASIC-level verification
  • Communicate and work with multi-disciplined and multi-site teams

Requirements For ASIC RTL Engineer, Silicon

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques

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