Chassis Power Architect, Silicon
Description For Chassis Power Architect, Silicon
Google is seeking a Chassis Power Architect to join their Silicon Platform IP Architecture team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products. The position involves collaborating with SoC and IP hardware architects to drive next-generation power management controller and chassis power optimization in advanced technology nodes, specifically for Google Tensor SoC and associated products.
The role requires deep expertise in power management and optimization, working on cutting-edge technology that impacts millions of users worldwide. You'll be responsible for defining power management controllers, deployment across SoC, and power optimization methods. The position involves charting power roadmaps for Chassis IPs, proposing optimization plans, and guiding both pre-silicon power modeling and post-silicon power correlation efforts.
As a Chassis Power Architect, you'll work at the intersection of hardware architecture and power optimization, making critical decisions that affect the performance and efficiency of Google's hardware products. The role offers the opportunity to work with state-of-the-art technology and tools, collaborating with cross-functional teams to develop innovative solutions for power management challenges.
The ideal candidate will bring strong technical expertise in power enhancement workflows, experience with power management IPs, and a deep understanding of low power design principles. This role is perfect for someone who wants to make a significant impact on the future of Google's hardware products while working with a diverse team that pushes boundaries in silicon development.
Responsibilities For Chassis Power Architect, Silicon
- Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment
- Come up with Power optimization methods for various chassis IP's
- Influence Power methodology for design, verification and implementation of deep submicron SoCs
- Develop innovative plans to achieve power optimization from circuit to system level
- Influence generic power management IPs to drive clock, reset, and power controls
Requirements For Chassis Power Architect, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in power enhancement workflow and techniques
- Experience with power management IPs
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design
- Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS
- Experience in post-silicon power calibrations and debug
- Experience in design and analysis of full chip power with understanding of clock, reset, and power sequencing interactions
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