Chassis Power Architect, Silicon
Description For Chassis Power Architect, Silicon
Google's Silicon Platform IP Architecture team is seeking a Chassis Power Architect to drive next-generation power management solutions for Google Tensor SoC and associated products. This role combines hardware architecture with power optimization expertise, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. You'll work on defining power management controllers, optimizing chassis power architecture, and balancing power vs performance tradeoffs. The position involves collaboration with SoC and IP hardware architects to drive innovation in advanced technology nodes. Google's mission to organize world's information is supported by this team's work in combining AI, Software, and Hardware to create helpful experiences. The role offers the opportunity to shape the future of Google's hardware experiences, working on products used by millions worldwide. The team emphasizes innovation, efficiency, and integration, making it an ideal position for those passionate about hardware architecture and power optimization.
Responsibilities For Chassis Power Architect, Silicon
- Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment
- Come up with Power optimization methods for various chassis IP's
- Influence Power methodology for design, verification and implementation of deep submicron SoCs
- Develop innovative plans to achieve power optimization from circuit to system level
- Influence generic power management IPs to drive clock, reset, and power controls
Requirements For Chassis Power Architect, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in power enhancement workflow and techniques
- Experience with power management IPs
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design
- Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS
- Experience in post-silicon power calibrations and debug
- Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions
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