Chassis Power Architect, Silicon
Description For Chassis Power Architect, Silicon
Google is seeking a Chassis Power Architect to join their Silicon Platform IP Architecture team. This role focuses on developing custom silicon solutions for Google's direct-to-consumer products, specifically working on power management and optimization for Google Tensor SoC and related products. The position involves collaborating with SoC and IP hardware architects to drive next-generation power management controller development and chassis power optimization in advanced technology nodes.
The ideal candidate will be responsible for defining power management controllers, optimizing power across the SoC, and developing power roadmaps for Chassis IPs. They will work closely with cross-functional teams to propose power optimization plans, guide pre-silicon power modeling, and manage post-silicon power correlation efforts. The role requires extensive experience in power enhancement workflows, management IPs, and deep understanding of low-power design techniques.
Working at Google, you'll be part of a diverse team that pushes boundaries and develops solutions that impact millions of users worldwide. The position offers the opportunity to shape the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. You'll be contributing to Google's mission of organizing world's information while working with cutting-edge technology and innovative teams.
The role requires strong technical expertise in power management, architecture development, and system-level optimization. You'll be working with various EDA tools, conducting simulations, and implementing power optimization strategies from circuit to system level. This is an excellent opportunity for someone passionate about hardware architecture and power optimization to make a significant impact on Google's future hardware products.
Responsibilities For Chassis Power Architect, Silicon
- Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment
- Come up with Power optimization methods for various chassis IP's
- Influence Power methodology for design, verification and implementation of deep submicron SoCs
- Develop innovative plans to achieve power optimization from circuit to system level
- Influence generic power management IPs to drive clock, reset, and power controls
Requirements For Chassis Power Architect, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in power enhancement workflow and techniques
- Experience with power management IPs
- Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design
- Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models
- Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS
- Experience in post-silicon power calibrations and debug
- Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions
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