Chipset Power Architect

Google is a global technology leader that develops innovative AI, software, and hardware solutions.
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
8+ years of experience
AI · Consumer · Hardware

Description For Chipset Power Architect

Google's Devices & Services team is seeking a Chipset Power Architect to join their innovative hardware development efforts. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As a Chipset Power Architect, you'll be responsible for defining and optimizing power requirements for System-on-Chip (SoC) designs, ensuring optimal performance while managing power constraints.

The position combines deep technical expertise in power architecture with strategic thinking, as you'll be involved from concept to mass production. You'll work with Google's cutting-edge AI, Software, and Hardware teams to create radically helpful experiences for users worldwide. The role involves sophisticated power modeling, analysis, and optimization techniques to advance Google's hardware capabilities.

This is an opportunity to shape the next generation of hardware experiences at one of the world's leading technology companies. You'll be part of a diverse team that pushes boundaries and develops solutions used by millions of people. The role requires a strong background in SoC power modeling and architecture, with the ability to drive critical decisions that balance power and performance requirements.

Working at Google's Bengaluru location, you'll contribute to the company's mission of organizing the world's information and making it universally accessible and useful through hardware innovation. The position offers the chance to work on challenging technical problems while collaborating with world-class engineers and researchers in Google's hardware division.

Last updated 4 days ago

Responsibilities For Chipset Power Architect

  • Define power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints
  • Define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals
  • Track power throughout the design cycle
  • Propose and drive power optimizations throughout the design process from concept to mass productization
  • Perform algorithm development, modeling, and analysis of various power approaches
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions

Requirements For Chipset Power Architect

  • Bachelor's degree in Electronics or Computer Engineering/Science, or equivalent practical experience
  • 8 years of experience with SoC power modeling and analysis
  • Experience with SOC architecture and power techniques
  • Master's degree or PhD in Electronics, Computer Engineering, or Computer Science (preferred)
  • Experience with ASIC design flows (preferred)
  • Experience with low power architecture and power optimization techniques (preferred)

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