Chipset Power Architect, Devices and Services, Silicon
Description For Chipset Power Architect, Devices and Services, Silicon
Google's Devices & Services team is seeking a Chipset Power Architect to join their innovative hardware development efforts. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As a Chipset Power Architect, you'll be responsible for defining and optimizing power requirements for System-on-Chip (SoC) designs, ensuring optimal Power-Performance-Area (PPA) metrics. You'll work at the intersection of hardware architecture and power optimization, contributing to products used by millions worldwide.
The position combines deep technical expertise in power modeling and analysis with strategic architectural decision-making. You'll be part of a diverse team that pushes boundaries in hardware development, working on next-generation devices that require sophisticated power management solutions. The role involves collaboration across various teams to guide architecture, design, implementation, and software development to achieve power goals.
This is an opportunity to shape the future of Google's hardware experiences, working with cutting-edge technology and contributing to products that make computing faster, more seamless, and more powerful. The ideal candidate will bring extensive experience in SoC power modeling and analysis, along with a strong understanding of power optimization techniques such as multi Vth/power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling.
The role offers the chance to work with Google's industry-leading AI, Software, and Hardware teams, contributing to radically helpful experiences for users. You'll be involved in the entire product development lifecycle, from concept to mass production, ensuring that Google's devices maintain optimal power efficiency while delivering unparalleled performance.
Responsibilities For Chipset Power Architect, Devices and Services, Silicon
- Define power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints
- Define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle
- Propose and drive power optimizations throughout the design process from concept to mass productization
- Perform algorithm development, modeling, and analysis of various power approaches
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions
Requirements For Chipset Power Architect, Devices and Services, Silicon
- Bachelor's degree in Electronics or Computer Engineering/Science, or equivalent practical experience
- 8 years of experience with SoC power modeling and analysis
- Experience with SOC architecture and power techniques
- Master's degree or PhD in Electronics, Computer Engineering, or Computer Science (preferred)
- Experience with ASIC design flows (preferred)
- Experience with low power architecture and power optimization techniques (preferred)
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