Chipset Power Architect
Description For Chipset Power Architect
Google's Devices & Services team is seeking a Chipset Power Architect to join their innovative hardware development efforts. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As a Chipset Power Architect, you'll be responsible for defining and optimizing power requirements for System-on-Chip (SoC) designs, ensuring optimal Power-Performance-Area (PPA) metrics under various constraints.
The position combines deep technical expertise in power architecture with strategic thinking, as you'll be guiding designs from concept through mass production. You'll work with cutting-edge technology, defining power KPIs, conducting sophisticated analysis, and driving critical decisions that impact product development.
The role offers an opportunity to work with Google's prestigious hardware team, contributing to products used by millions worldwide. You'll be part of a diverse team that pushes boundaries in custom silicon development, working at the intersection of hardware innovation and power efficiency.
This position is perfect for experienced professionals with a strong background in SoC power modeling and architecture. You'll have the chance to shape the next generation of Google's hardware experiences, focusing on delivering unparalleled performance and efficiency. The role combines technical leadership with hands-on engineering, requiring both strategic thinking and detailed technical knowledge.
Working at Google means joining a company committed to innovation and inclusive technology development. You'll be part of a team that values diverse perspectives and focuses on creating radically helpful experiences for users worldwide. The position offers the opportunity to work on challenging problems while contributing to products that make a real difference in people's lives.
Responsibilities For Chipset Power Architect
- Define power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints
- Define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle
- Propose and drive power optimizations throughout the design process from concept to mass productization
- Perform algorithm development, modeling, and analysis of various power approaches
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions
Requirements For Chipset Power Architect
- Bachelor's degree in Electronics or Computer Engineering/Science, or equivalent practical experience
- 8 years of experience with SoC power modeling and analysis
- Experience with SOC architecture and power techniques
- Master's degree or PhD in Electronics, Computer Engineering, or Computer Science (preferred)
- Experience with ASIC design flows (preferred)
- Experience with low power architecture and power optimization techniques (preferred)
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